Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-01-26
2001-02-27
Auve, Glenn A. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06195722
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the transfer of information on a host bus. More particularly, the invention relates to a method and apparatus for third party agent transaction deferral on a host bus.
BACKGROUND OF THE INVENTION
In a typical computer system, such as a personal computer, a processor can communicate with peripherals, such as a memory subsystem, a graphics subsystem or another processor in the computer system, over an information path referred to as a “host” bus. The host bus carries “transactions,” such as requests to read or write information, between devices that communicate on the host bus. One or more processors in the computer system are generally attached directly to the host bus.
In addition to one or more processors, a group of integrated circuits, called a “chip set,” can be attached directly to the host bus. The chip set also communicates with peripherals, such as a graphics subsystem, attached to a “local” bus and a memory subsystem. A bus that complies with a Peripheral Component Interconnect (PCI) standard (e.g., PCI Local Bus Specification, Version 2.1, a copy of which can be obtained from the PCI Special Interest Group in Portland, Oreg.) is an example of such a local bus. If a peripheral attached to the PCI bus wishes to send a transaction to a processor, the transaction is sent from the peripheral to the chip set over the PCI bus. The chip set then forwards the transaction to the appropriate processor over the host bus.
The processors and the chip set are commonly referred to as “agents” on the host bus. In addition to one or more processors and the chip set, a Third-Party Agent (TPA) can also be connected to the host bus. An optional cluster bridge that connects a first computer system to a second computer system, generally by communicating with another cluster bridge on the second computer system's host bus, is an example of such a TPA. This arrangement has the advantage of increasing the number of processors that can work together. For example, if the host bus can only support four processors, a cluster bridge TPA allows the first computer system to communicate with other processors in the second computer system, letting more than four processors work together. In this case, peripherals on the PCI bus of the first computer system can direct transactions to, for example, a processor in the second computer system through the TPA.
Transactions from the PCI bus are typically performed in the order they are received by the chip set. Assume, for example, that the chip set receives a first transaction requesting to write information to the TPA from the PCI bus. Next, the chip set receives a second transaction requesting to send data to the memory subsystem from the PCI bus. In this case, the first transaction would normally be completed before the second transaction is acted upon. Note that the two transactions could originate from the same peripheral or from different peripherals on the PCI bus.
This “in order” execution scheme, however, can cause a problem when the first transaction cannot be completed in a timely manner. Suppose, in the above example, that the TPA is not able to immediately complete the first transaction, perhaps because the TPA is temporarily busy communicating with a second computer system. If the second transaction is simply held up until the first transaction is completed, in effect all of the devices attached to the host bus are waiting for the TPA, even though those devices do not need to use the TPA. This obviously has a negative impact on the performance of the host bus and on the computer system as a whole.
To avoid this problem, it is known to have the TPA indicate that a particular transaction should be “retried” at a later point in time. The transaction is retried at a later point in time by being resent to the TPA over the host bus. This allows the other devices on the host bus to continue to work when the TPA is busy, improving system performance. The retry method is called an “out of order” execution scheme because in effect the transactions are not being performed in the order that they were originally requested—the agent on the host bus that originally issued the transaction request is forced to re-issue the request at a later time.
The retry solution, however, also has a disadvantage. It is possible that a device, such as a peripheral on the PCI bus, will retry a transaction immediately after the TPA indicates that it is unable to perform that transaction. In this case, depending on the length of time that the TPA is busy, the host bus could become flooded with retry requests for the same transaction. This also would have a negative impact on system performance, because unnecessary transactions on the host bus prevent the agents from communicating with each other.
With respect to processors on the host bus, this problem has been addressed by using a different out of order execution scheme. In this case, the processor “defers” a transaction request, as opposed to having the request retried. When a transaction is deferred, the processor will eventually perform the transaction without the agent re-sending the command on the host bus. When the processor later performs the transaction, it informs the agent that generated the original transaction request by sending a “defer reply” over the host bus. Previously, there has been no similar way for a TPA to defer a transaction on the host bus. Moreover, a transaction deferral scheme cannot simply be added to existing TPA and chip set logic because, for example, the chip set would have no way of tracking and identifing the out of order deferred transactions and their associated defer replies.
In view of the foregoing, it can be appreciated that a substantial need exists for a method and apparatus that reduces unnecessary transactions and delays involving a TPA on a host bus, and solving the other problems discussed above.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, a transaction request is received from a device, and transaction information related to the transaction request is stored. An indication is received from a third party agent that the transaction has been deferred, and the stored transaction information is updated to reflect that the transaction has been deferred.
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Chittor Suresh S.
Jackson David R.
Looi Lily Pao
Ram Rajee
Auve Glenn A.
Intel Corporation
Kenyon & Kenyon
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