Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-12-04
2001-01-09
Etienne, Ario (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S107000, C710S118000, C710S125000, C710S220000
Reexamination Certificate
active
06173354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to bus bridges, and specifically, to a method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus.
2. Background Information
In a typical computer system, a central processing unit or microprocessor, on a host bus, is coupled to system memory and one or more devices on a secondary bus by way of a bus bridge. The bus bridge bridges transactions between the microprocessor, one or more devices on the secondary bus, and the system memory. The bus bridge also decouples the microprocessor from activities between the system memory and the secondary bus. When the microprocessor attempts a write cycle to, for example, system memory, it waits for the assertion of target ready (TRDY#) by the bus bridge before initiating the transfer of data on the host bus. The P
6
Bus Protocol, Revision 4, published in August 1995 by Intel® Corporation of Santa Clara, Calif., allows for the assertion of TRDY#, at the earliest, four clock cycles from the beginning of the cycle. When the bus bridge is the target of a microprocessor initiated write cycle, it has to take the following actions before it can assert TRDY# on the host bus: (i) Decode the cycle and determine its destination; (ii) assert a request to the destination unit and wait for a response back from that destination unit; and (iii) if the destination unit is capable of accepting the data, assert TRDY# on the host bus. At 100 Mhz, for example, the response from the destination unit can be received, at the earliest, in T
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. This pushes out the assertion of TRDY# to T
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and, subsequently, the data transfer is pushed out by a clock relative to the earliest possible transfer point. It would be desirable to minimize the amount of latency involved in such a cycle.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus. In one embodiment, the method includes detecting a write cycle by an initiator to transmit data to a device, asserting a write request to the device, responsive to detecting the write cycle, and asserting a ready request to the initiator without detecting an acknowledge from the device. The method further includes receiving the data from the initiator.
REFERENCES:
patent: 5070443 (1991-12-01), Priem et al.
patent: 5448742 (1995-09-01), Bhattacharya
patent: 5734856 (1998-03-01), Wang
patent: 5748914 (1998-05-01), Barth et al.
International Search Report, PCT/US99/26728, 4 pages.
Bogin Zohar
Clohset Steve
Khandekar Narendra
Blakely , Sokoloff, Taylor & Zafman LLP
Etienne Ario
Intel Corporation
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