Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-18
2009-06-16
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S120000, C700S121000, C430S005000, C378S035000
Reexamination Certificate
active
07549140
ABSTRACT:
A method of generating a mask of use in printing a target pattern on a substrate. The method includes the steps of (a) determining a maximum width of features to be imaged on the substrate utilizing phase-structures formed in the mask; (b) identifying all features contained in the target pattern having a width which is equal to or less than the maximum width; (c) extracting all features having a width which is equal to or less than the maximum width from the target pattern; (d) forming phase-structures in the mask corresponding to all features identified in step (b); and (e) forming opaque structures in the mask for all features remaining in target pattern after performing step (c).
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Broeke Doug Van Den
Chen Jang Fung
Hsu Stephen
Laidig Thomas
Wampler Kurt E.
ASML Masktools B. V.
Kik Phallaka
Pillsbury Winthrop Shaw & Pittman LLP
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