Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2011-08-09
2011-08-09
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07996752
ABSTRACT:
In a decoder for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes, a method is provided. The method comprises the steps of: providing a memory for the decoding with the memory dependent on a parity check matrix H with maximum number of “1”s; using a number of column updating units, updating columns parallely and simultaneously producing messages; and using a number of row updating units, updating rows parallely and simultaneously producing messages. Whereby an improved architecture in a logic and the memory is provided such that an improved throughput, power consumption, and memory area is achieved.
REFERENCES:
patent: 7178080 (2007-02-01), Hocevar
Prabhakar Abhiram
Zhong Yan
Chase Shelly A
Legend Silicon Corp.
Tian Frank F.
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