Method and apparatus for decimal number multiplication using...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S495000, C708S503000, C708S625000

Reexamination Certificate

active

07912890

ABSTRACT:
According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

REFERENCES:
patent: 7069289 (2006-06-01), Steele, Jr.
patent: 7395297 (2008-07-01), Steele, Jr.
patent: 7519645 (2009-04-01), Carlough et al.
patent: 7519647 (2009-04-01), Carlough et al.
patent: 7546328 (2009-06-01), Schulte et al.
patent: 7577699 (2009-08-01), Denk et al.
patent: 2007/0233774 (2007-10-01), Tang et al.
patent: 2007/0266073 (2007-11-01), Cornea-Hasegan
Gonzalez-Navarro, S.; Tsen, C.; Schulte, M., “A Binary Integer Decimal-based Multiplier for Decimal Floating-Point Arithmetic,” Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, pp. 353-357, Nov. 2007.
Tsen, C.; Schulte, M.; Gonzalez-Navarro, S., “Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit,” IEEE International Conf. on Application-specific Systems, Architectures and Processors, pp. 115-121, Jul. 2007.
Intel Inc., “Reference Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic”, retrieved from http://cache-www.intel.com/cd/00/00/29/43/294339—294339.pdf.
Marius Cornea and Cristina Anderson, “Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic,” in Proceedings, Real Numbers and Computers Conference, 2006.
European Patent Office, Search Report issued in connection with the corresponding EP Application No. 07251933.3, 7 pages, Nov. 11, 2008.
Ref1-Anonymous: “Draft Standard for Floating-Point Arithmetic P754/D0.17.4—May 9, 2006 15:13” [Online] May 9, 2006 IEEE , Piscataway, NJ, USA , XP002498605 Retrieved from the Internet: URL:754r.ucbtest.org/drafts/archive/2006-0 5-09.pdf> [retrieved on Oct. 6, 2008] pp. 8,40,211 pp. 126-143.
Ref1-Anonymous: “Index of /drafts/archive” [Online] 2006, IEEE , XP002498606 Retrieved from the Internet: URL:754r.ucbtest.org/drafts/archive> [retrieved on Oct. 8, 2008].
Ref2-K. DUKE: “Decimal Floating Point Processor. Nov. 1969.” IBM Technical Disclosure Bulletin, vol. 12, No. 6, Nov. 1, 1969, p. 862, XP002498604 New York, US.
Ref3-Liang-Kai Wang et al: “Decimal floating-point division using newton-raphson iteration” Application-Specific Systems, Architectures and Processors, 2004. Proc eeings. 15th IEEE International Conference on Galveston, TX, USA Sep. 27-29, 2004, Piscataway, NJ, USA,IEEE, Sep. 27, 2004, pp. 84-95, XP010730170 ISBN: 978-0-7695-2226-5.
Ref4-Johnstone P et al: “Higher radix floating point representations” Computer Arithmetic, 1989., Proceedings of 9th Symposium on Santa Monica, CA, USA Sep. 6-8, 1989, Washington, DC, USA, IEEE Comput. Soc. PR, US, Sep. 6, 1989, pp. 128-135, XP010033234 ISBN: 978-0-8186-8963-5.
European Patent Office, Communication Pursuant to Article 94(3) EPC, dated Feb. 25, 2009 in a related application.
Anonymous, “Draft Standard For Floating-Point Arithmetic P754/D0.17.4-May 9, 2006 15:13,” pp. 1-248.
K. Duke, “Decimal Floating Point Processor,” Nov. 1969, IBM Technical Disclosure Bulletin, vol. 12, No. 6, Nov. 1, 1969, p. 862.
Mark A. Erle, et al, “Decimal Multiplication With Efficient Partial Product Generation,” 2005, pp. 1-8.
Pending U.S. Appl. No. 11/133,811, filed May 19, 2005, Inventor: Marius A. Cornea-Hasegan.
Hollasch: IEEE Standard 754 Floating Point Numbers; ret'd from the web http://steve.hollasch.net/cgindex/coding/ieeefloat.html; last update Dec. 4, 2001; 7 pages.
U.S. Patent and Trademark Office, Office Action issued on Dec. 29, 2009 ,with Reply to Office Action filed on Mar. 29, 2010 in U.S. Appl. No. 11/432,808.
European Patent Office, Communication Pursuant to Article 94(3) EPC dated Jan. 19, 2010 in European patent application No. 07 251 933.1-1229.
Gerd Bohlender, “Decimal Floating-Point Arithmetic In Binary Representation,” 1991, pp. 1-15.

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