Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-08-30
2010-10-19
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S027000, C714S031000
Reexamination Certificate
active
07818619
ABSTRACT:
A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations on the SUT via the memory mapping interface bus. The debugging processor and the SUT processor operate together in a cluster mode to provide non-invasive debugging of the (SUT) while the SUT executes application software in a real time environment.
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Beausoliel Robert
International Business Machines - Corporation
Kahler Mark P
Manoskey Joseph D
Talpis Matt
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