Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-09-12
2006-09-12
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S027000
Reexamination Certificate
active
07107489
ABSTRACT:
A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.
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Dao Tan Nhat
Gergen Joseph P.
Hannah Jerome
Baderman Scott
Clingan, Jr. James L.
Contino Paul
Freescale Semiconductor Inc.
Hill Susan C.
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