Method and apparatus for deadlock prevention in a...

Details Method and apparatus for deadlock prevention in a... Method and apparatus for deadlock prevention in a...

2005-03-08

2005-03-08

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

C710S107000, C710S108000, C711S163000

Reexamination Certificate

active

06865634

ABSTRACT:
A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes, in each coherency controller of each of the memories in the system, a mechanism to reserve at least one slot of the memory access request transaction queue for exclusive processing of processor return (PR) transactions to provide an uninterrupted processing of PR transactions. The number of blocking (BL) transaction is limited to a number less than available slots. The distributed shared memory system also includes a distributed memory return transaction queue that allows each of entries in the memory access request transaction queue to add a plurality of memory return transactions per clock cycle.

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