Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2000-10-10
2004-09-07
Phu, Phuong (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S373000, C327S158000, C713S401000, C713S503000
Reexamination Certificate
active
06788754
ABSTRACT:
BACKGROUND
When operating microprocessors and other digital equipment embodied within integrated circuits (ICs), it is generally desirable to coordinate and/or synchronize the transmission of signals from clocks distributed throughout such chips. Such synchronization would generally aid in enabling related operations to cooperate in a timely and orderly manner. Undesired and unpredictable variation in the propagation times of signals along different paths could lead to race conditions and other malfunctions in the operation of the microprocessor or other integrated chip device.
As chips become larger, more complex, and more powerful, the number of factors potentially causing variation in signal transmission speed along different paths within an IC generally increases. These factors include, voltage levels, current flow levels, operating frequency, and temperature. Other factors contributing to variation in signal transmission speed include variation in the geometric length of the signal paths and inconsistency of electrical properties such as resistance and capacitance which may be encountered by different signals propagating through different parts of an integrated chip. Even though attempts have been made to balance the signal transmission delays on various clock routes in order to equalize propagation times along these routes, the unpredictability of many of the above-mentioned factors makes it extremely difficult to fully maintain signal transmission delay consistency across different signal paths.
Another approach to equalizing transmission path delays involves inserting delay circuits such as phase lock loops (PLLs) or delay lock loops (DLLs) within selected transmission paths to compensate for variation arising from known factors causing transmission path delay divergence within a chip. Where causes of transmission time or transmission delay divergence between different paths in a circuit are known and fixed, such circuits may present a viable solution. However, where variations in transmission time are variable and unknown, an initial setting of the delay circuits will likely fail to assure consistency in signal propagation time along various transmission paths. Factors which are likely difficult to ascertain in advance include process variation from one chip to another, as well quantities such as voltage, current, and temperature, which may vary from chip to chip, as well as within a single chip. It would therefore be very difficult to preset the values of delay circuits to achieve transmission time consistency among a plurality of signal transmission paths.
Accordingly, it is a problem in the art that variation in voltage and current levels, temperature, and electrical properties of various transmission paths generally cause alternate signal transmission paths in an IC to experience divergent transmission delays or latency periods.
It is a further problem in the art that such divergent latency periods may lead to race conditions and potentially cause malfunctions within an IC.
It is a still further problem in the art that strategically arranging the geometry of signal transmission paths generally does not cure the problem of inconsistent signal transmission path latency.
It is a still further problem in the art that introducing circuit elements for delaying signal transmission to compensate for variability in signal path transmission latency is generally unable to compensate for signal path latency differences arising from chip manufacturing process variation, and from variation in voltage, current, and temperature.
SUMMARY OF THE INVENTION
The present invention is directed to a system and method for providing self-governing real-time feedback signal path latency equalization to synchronize the transmission of signals propagating along separate paths in an integrated circuit. The inventive mechanism preferably provides for automatic self-regulating phase or delay equalization in a manner which is independent of the cause or amount of propagation time delay variation between alternative signal transmission paths.
In a preferred embodiment, feedback loops are employed which receive signal delay values as inputs and generate a corrective output signal substantially proportional to a disparity in the input delay values, thereby enabling a magnitude of a corrective output signal to a level suited to a current level of signal transmission time disparity. In this manner, a delay circuit designed to compensate for a transmission signal time difference between two circuits may be continuously adjusted in real time to compensate for real time variations in the factors leading to this transmission signal time variation. Since the inventive circuit employs the actual signal delay variation as an input variable for a determination of a delay value, all causes of this signal delay variation are preferably compensated for regardless of the sources of the delay. Accordingly, there is preferably no need to conduct complex calculations to anticipate desired signal delay values within particular signal transmission paths.
In a preferred embodiment, the self-governing delay equalization circuits of the present invention may be scattered throughout a chip so as to equalize delays in distributed locations and thereby avoid imposing an excessive delay equalization burden in a single centralized location. Moreover, the careful deployment of phase detectors and other selected circuit elements may be beneficially employed to reduce electrical noise along the various signal paths while also equalizing delays along these signal paths. Moreover, the implementation of self-governing delay equalization may be applied to subsets of an initial set of circuits, thereby enabling the creation of a hierarchy of delay-equalized sub-circuits having equal signal transmission delay times. In this manner, the signal delay present at a multitude of points throughout an IC, with respect to one or more time reference points or clock reference points may be determinable with substantial accuracy.
It will be appreciated that while much of the above discussion herein is directed to integrated circuits and digital equipment, the present invention may be applicable to any circuit having undesired transmission time variations between alternative signal paths including analog circuits, hybrid circuits, and circuits which are not solid state, and all such variations are included within the scope of the present invention.
Accordingly, it is an advantage of a preferred embodiment of the present invention that signal path transmission delays arising from substantially unpredictable sources such as temperature, voltage, and current fluctuations may be adaptively compensated for in real time without knowing the sources or relative magnitude of contribution to a resulting delay of each of the afore-mentioned sources.
It is a further advantage of a preferred embodiment of the present invention that race conditions and other operational problems arising from signal path transmission time or transmission delay variations may preferably be avoided.
It is a still further advantage of a preferred embodiment of the present invention that the inventive self-governing signal path delay equalization circuit may be employed to reduce electrical noise levels along the various signal transmission paths. The ability to control when clock edges occur generally allows a system designer to deliberately skew circuit clock edges to prevent circuits employing those clock edges from switching simultaneously, thereby reducing instantaneous power and electrical noise.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modi
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