Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2001-03-28
2004-10-26
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C327S147000
Reexamination Certificate
active
06810486
ABSTRACT:
FIELD
The present invention relates to a multiple clock domain de-skewing technique. More particularly, the present invention relates to a multiple clock domain de-skewing technique utilizing dual PLL (Phase Locked Loop) loops to de-skew clock signals of three different domains.
BACKGROUND
There are many systems, such as an MPT (Memory Protocol Translator), which transfer data between two different systems, such as two different memory systems. Using the two memory system and MPT arrangement as an example, there are three different clock signal domains, namely, the clock signals of each of the two memory systems and the clock signals of the MPT. In order for the arrangement to operate properly, the three different clock signals must be de-skewed.
FIG. 1
illustrates an example of an earlier disadvantageous arrangement for de-skewing clock signals. As shown in
FIG. 1
, a memory system, such as SDRAM (Synchronous Dynamic Random Access Memory)
170
is connected to an MPT
100
via transmission lines
171
,
172
,
173
,
174
, and
175
and a CLK BUFF (Clock Buffer)
160
. The clock outputted by the MPT clock output buffer
151
is inputted through transmission line
171
to the clock buffer
160
. The clock buffer
160
has one output which is inputted to the SDRAM
170
via transmission line
175
and has another output which is fed back to the MPT
100
via transmission line
172
. The two outputs of the clock buffer
160
are substantially identical.
Contained within the MPT
100
are flip-flops
120
and
130
which respectively output and input RDRAM data to an output flip-flop
150
and an input flip-flop
140
. The feedback clock inputted to the MPT
100
from the transmission line
172
is inputted to a clock tree
180
via an input clock buffer
152
. The output clock CLK of the clock tree
180
is used to clock both the output and input flip-flops
150
and
140
and is also inputted to a PLL
110
. The output of the output flip-flop
150
is inputted to the SDRAM
170
via an output buffer
153
and the transmission line
173
. The output of the SDRAM
170
is inputted to the input flip-flop
140
via the transmission line
174
and an input buffer
154
.
The phase of the clock CLK is adjusted by the PLL
110
so as to match the phase of the reference clock rclkref of the MPT
100
. Ideally, the clock inputted to the SDRAM
170
via the transmission line
175
should always be in phase with respect to the clock CLK to insure the proper transmission of data between the MPT
100
and the SDRAM
170
. Unfortunately, in reality, this is not the case since the path for the clock from the output of the PLL
110
to the SDRAM
170
is different than the path of the clock outputted from the PLL
110
to the output of the clock tree
180
. Since the paths are different, there are differences in phase which are dependent upon the behavior of the clock buffer
160
and the characteristics of the clock tree
180
. That is, ideally, the clock which is inputted to the SDRAM
170
via the transmission line
175
should begin at the same time as the clock inputted to the output flip-flop
150
. However, the delays in the transmission lines
171
,
172
, and
175
may vary as will the delays in the CLK BUFF
160
and the clock output buffer
151
, clock input buffer
152
, and the clock tree
180
. These delays will vary over time due to changes in ambient conditions and aging and will also vary from element to element. The characteristics of the clock tree
180
will vary from one integrated circuit die to another due to process variations as well as varying over time due to voltage variations and temperature variations.
Thus, while the internal MPT clock CLK is de-skewed (that is, in phase) with respect to the reference clock rclkref (the clock of the RDRAM interface), the input/output clock is not in phase with the SDRAM clock and due to the clock skew, it is fairly difficult to meet the AC timing requirements (e.g.—minimum and maximum output delay, setup time, and hold time) on the SDRAM interface.
REFERENCES:
patent: 6127865 (2000-10-01), Jefferson
patent: 6239627 (2001-05-01), Brown et al.
patent: 6625559 (2003-09-01), Helder
IBM, Nested Phase-lock Loops for Board Level Clocking, Jun. 1, 1994, IBM Technical Disclosure Bulletin, vol. 37 Issue 6A, pp. 349-352.
Fayneh Eyal
Knoll Earnest
Butler Dennis M.
Connolly Mark
LeMoine Patent Services, PLLC
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