Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2001-12-07
2002-09-24
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S203000
Reexamination Certificate
active
06456545
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a method and an apparatus for data transmission and reception and more specifically to a method and an apparatus in which an offset voltage may be prevented on a floating capacitance in a connection node between a first transfer device and a second transfer device.
BACKGROUND OF THE INVENTION
A conventional semiconductor memory device may have a column select transfer gate for transferring a data bit signal amplified in a sense amplifier to a data bus.
Referring now to
FIG. 1
, a portion of conventional semiconductor memory device is set forth in a schematic diagram and given the general reference character
100
.
Conventional semiconductor memory device
100
is formed on a semiconductor substrate
10
S. Conventional semiconductor memory device
100
includes a column select transfer gate circuit
11
connected to data buses (IOT and ION) and bit line pairs (D
1
and DB
1
to Dn AND DBn). Transfer gate circuit
11
also is connected to receive column select signal PYU and column select signals (YL
1
to YLn). Column select transfer gate circuit
11
is arranged such that column select transfer gates (M
1
i
and M
2
i
) are connected in series between bit line Di and column select transfer gates (M
1
Bi and M
2
Bi) are connected in series between bit line DBi (i can be a number between 1 and n, where n is the number of columns of memory cells illustrated). N-type MOSFETs (metal oxide semiconductor field effect transistors) are used for column transfer gates (M
1
i
, M
2
i
, M
1
Bi, and M
2
Bi). A bit line pair (Di and DBi) transmits complementary binary data signals indicating the logic value of one data bit.
A parasitic capacitor (Ci and CBi) is formed at the connection point of series connected column select transfer gates (M
1
i
-M
2
i
and M
1
Bi-M
2
Bi) and is illustrated having one node connected to the connection point and another node connected to ground.
A column address decode circuit
13
receives and address signal from a command bus pad
10
CMD and generates column select signal PYU and column select signals (YL
1
to YLn). Column select signal PYU is received at a gate of each column select transfer gate (M
11
to M
1
n
and M
1
B
1
to M
1
Bn). Column select signal YLi is received at a gate of each column select transfer gate (M
2
i
and M
2
Bi). Column select signal PYU and column select signal YLi are supplied simultaneously from address decode circuit
13
. Address decode circuit
13
decodes a column address received with an access command when accessing conventional semiconductor memory device
100
.
A sense amplifier Si is connected between bit line pair (Di and DBi). Bit line Di is electrically connected to data bus IOT when column select transfer gates (M
2
i
and M
1
i
) are turned on. Bit line DBi is electrically connected to data bus ION when column select transfer gates (M
2
Bi and M
1
Bi) are turned on.
Data buses (IOT and ION) are connected to a precharge circuit
15
and data bus pad
10
DB on semiconductor substrate
10
S.
A description of the operation of conventional semiconductor memory device
100
will now be described with reference to
FIGS. 1 and 2
.
FIG. 2
is a timing diagram illustrating the operation of conventional semiconductor memory device
100
for various cycles. Column select transfer gates (M
1
i
, M
2
i
, M
1
Bi, and M
2
Bi) of conventional semiconductor memory device
100
operate as follows.
When no access to the conventional semiconductor memory device
100
is taking place, column address decode circuit
13
outputs column select signal PYU and column select signal YLi having a low level.
With column select signal PYU and column select signal YLi at a low level, column select transfer gates (M
1
i
, M
2
i
, M
1
Bi, and M
2
Bi) are all turned off and bit line pair (Di and DBi) are not electrically connected to data buses (IOT and ION), respectively.
When a write command W is received by conventional semiconductor memory device
100
as an external input command, a column address in the write command (W in
FIG. 2
) is supplied to column address decode circuit
13
through command bus pad
10
CMD. Column address decode circuit
13
generates a column select signal PYU and column select signal YLi having a high level accordingly.
With column select signal PYU and column select signal YLi at a high level, column select transfer gates (M
1
i
, M
2
i
, M
1
Bi, and M
2
Bi) are all turned on and bit line pair (Di and DBi) are electrically connected to data buses (IOT and ION), respectively. In this way, data may be transferred from data buses (IOT and ION) to bit line pair (Di and DBi) and written into a memory cell (not shown) that is connected to bit line pair (Di and DBi) and that has already been turned on in response to a row address.
Subsequently, at the end of the write operation, column select signal PYU and column select signal YLi are simultaneously switched from the high level to the low level. With column select signal PYU and column select signal YLi at a low level, column select transfer gates (M
1
i
, M
2
i
, M
1
Bi, and M
2
Bi) are all turned off and bit line pair (Di and DBi) are not electrically connected to data buses (IOT and ION), respectively. In this way, connection nodes having parasitic capacitors (Ci and CBi) become floating and charge stored on parasitic capacitors (Ci and CBi) becomes trapped or stored.
Subsequently, the data buses (IOT and ION) are precharged with precharge circuit
15
in response to a precharge command (P in
FIG. 2
) supplied through command bus pad
10
CMD. Data busses (IOT and ION) are precharged to an intermediate level (precharge level). However, at this time, connection nodes having parasitic capacitors (Ci and CBi) remain floating and can have different voltages in accordance with the logic value of data previously written.
Subsequently, when a read command (R in
FIG. 2
) is received by conventional semiconductor memory device
100
, address decode circuit
13
supplies a column select signal PYR and column select signal YLi having a high level in response to a column address.
In the read command, a row address is supplied to a row address decode circuit (not shown) and a row of memory cells (not shown) are selected. Sense amplifiers (S
1
to Sn) amplify data received from the memory cells. Thus, a row of memory cells is simultaneously selected.
When column select signals (PYR and YLi) become high, the connection nodes having parasitic capacitors (Ci and CBi) become electrically connected to bit line pair (Di and DBi) and data buses (IOT and ION). Because parasitic capacitors (Ci and CBi) can have different voltage potentials as previously described, an offset voltage can be produced on the data buses (IOT and ION). This offset can affect the access speed and/or logic integrity of data supplied from sense amplifier Si and read out on data buses (IOT and ION).
Japanese Laid-Open Patent Publication No. 2000-149571 (JP 2000-149571) discloses a conventional semiconductor integrated circuit device.
JP 2000-149571 discloses a conventional semiconductor integrated circuit device including bit line pairs divided into groups having different capacitance values. A charge transfer device is included to separate bit line pairs. The charge transfer device is switched off before electric charge is provided to bit line pairs and a sense amplifier in a read operation.
A reference electric potential supply circuit is provided and a charge transfer device is switched on to provide charge to a connection point including a parasitic capacitor (for example, Ci and CBi). Then the other charge transfer device is turned on to supply electric charge to a detection/amplification line.
However, similarly as discussed above, the conventional semiconductor integrated circuit device disclosed in JP 2000-149571 has a drawback in that after a write operation in which data is written, electric charge is stored or trapped on capacitors (Ci and CBi) which are floating. During a subsequent read cycle, the signal provided by the electric charge is stor
Lam David
NEC Corporation
Walker Darryl G.
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