Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2001-09-25
2004-11-16
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000, C365S202000, C365S201000, C365S189070
Reexamination Certificate
active
06819611
ABSTRACT:
TECHNICAL FIELD
This invention relates to integrated circuit memory devices, and, more particularly, to a method and apparatus for reading data from memory devices in a compressed manner to expedite testing of memory devices.
BACKGROUND OF THE INVENTION
Integrated circuits are extensively tested both during and after production and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as dynamic random access memories (“DRAMs”), are tested during production at the wafer level and after packaging, and they are also routinely tested each time a computer system using the DRAMs executes a power up routine when power is initially applied to the computer system. DRAMs are generally tested by writing known data to each location in the memory, reading data from each memory location and then determining if the read data matches the written data. As the capacity of DRAMs and other memory devices continues to increase, the time required to write and then read data from all memory locations continues to increase, even though memory access times continue to decrease.
Various proposals have been made to decrease the time required to test memory devices, such as DRAMs. The time required to write known data to memory devices has been reduced by such approaches as simultaneously writing the same data to each column of each array in the memory device one row at a time. Other approaches include internal circuitry for transferring data from each column of one row to the next without requiring the memory to be addressed. These approaches have reduced the time required to write known data or a known pattern of data to the memory array.
Solutions have also been proposed for reducing the time required to read data from memory devices so that the data can be compared to the data written to the memory devices. One approach to solving the problem of excessive read times relies on data compression in which data from a direct current sense amplifier for one memory array are internally compared to the data from a sense amplifier of a different memory array. Simultaneously reading data from different memory locations in two different arrays has significantly reduced the time required to read data from memory devices for test purposes. However, combining data from multiple sense amplifiers requires the addition of circuitry and conductors to couple the outputs of the multiple sense amplifiers to comparison circuitry. As the circuit features of semiconductor devices become more densely packed, there is less space available to route conductors from each sense amplifier to a single location and to provide additional circuitry to combine the outputs of the direct current sense amplifiers.
There is therefore a need to be able to read data from a memory device in a compressed form to reduce testing time that can be implemented on integrated circuits having very densely packed circuit features.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a test circuit is included in a memory device having at least one array or bank of memory cells arranged in rows and columns, a pair of complementary digit lines for each column and a direct current sense amplifier that couples data from a digit line selected by a column address to an external data terminal of the memory device. In accordance with one aspect of the invention, the test circuit includes a direct current sense amplifier that also provides a wired-OR function combining data from several digit lines to one set of complementary I/O lines. When data from one memory cell differs from data from another cell and these data are being combined, both of the complementary I/O lines are low, and a detector circuit produces a “fail” signal. As a result, data can be read from the array in compressed fashion, e.g. from two columns at a time, thereby increasing the rate at which the memory array can be tested after background data have been written to the array. Although the memory device may have only a single memory array, it may also have multiple arrays, in which case columns from different arrays may be coupled to the inputs of a DC sense amplifier in the test mode. The coupling between the inputs of the DC sense amplifier and the digit lines is preferably through a pair of data lines coupled to the inputs of the DC sense amplifier, a pair of I/O lines for each of the arrays to which the digit lines of an addressed column are connected and a multiplexer selectively coupling two of the I/O lines to the data lines.
In accordance with an aspect of the invention, the test circuit may be used in a memory device that is connected to a test system. In such case, the test system may first write a known pattern of background data to the array followed by reading data from pairs of different columns of the memory device, as explained above. The read data are then examined to determine if the read data correspond to the pattern of background data written to the array, thereby providing an indication of whether the memory device is operating properly.
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Dorsey & Whitney LLP
Nguyen Viet Q.
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