Method and apparatus for data alignment and parsing in SIMD...

Electrical computers and digital processing systems: processing – Processing control – Logic operation instruction processing

Reexamination Certificate

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C712S204000, C712S208000, C712S300000, C712S002000

Reexamination Certificate

active

10403152

ABSTRACT:
Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and a second subset of data of less than n bits are selected, by logical shifting, from the two registers, respectively, based solely upon the shift value. Then, the subsets are concatenated, preferably by a logical OR, to obtain an output of n bits. The output may be aligned data or packed data, particularly useful for performing a single operation on multiple sets of the data through parallel processing with a SIMD processor.

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