Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-01-26
2004-11-02
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C370S366000
Reexamination Certificate
active
06813734
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of network systems and, more specifically, to data aligners used in network systems.
BACKGROUND
The Internet may be described in a simplified manner as a collection of computer systems that are interconnected by networks (e.g., transmission lines, switches and routers) to enable the transfer of data among the computer systems. Data is typically transmitted in networks along a data path in the form of data packets. An important characteristic of a data path is bit width. Bit width is the number of bits manipulated or passed contemporaneously on the data path. The bit width of a data path determines its bandwidth along with clock speed. Bandwidth is a measure of how fast data flows on the data path. In digital systems, bandwidth may be expressed as data speed in bits per second (bps).
At one time data was exclusively carried on a traditional Plain-Old Telephone System (POTS), or Public Switched Telephone Network (PSTN), using copper wire transmission lines that have limited bandwidth capability. Later, other types of networks were developed using higher bandwidth transmission lines that enabled greater amounts of data to be transmitted over a given time (higher bps), for example, an Integrated Services Digital Network (ISDN). ISDN provides digital transmission over ordinary PSTN copper wires on a narrow band local loop.
Higher bandwidths are the need of the time given the explosive growth and doubling of data traffic over the Internet. Two solutions for meeting the need for increased bandwidths are higher clock speeds and wider data paths. System designers are capitalizing on technology advancements by running the data path at higher clock speeds. System designers are also increasing the bit width to make data paths wider. Despite wider data paths, these systems still may be required to support legacy systems, i.e., older systems designed earlier on narrower data paths. Thus, the use of wider data paths may lead to data stream irregularities.
Other important parameters associated with a data path are the type of network and protocol used to transmit data on the data path. Computer systems communicate with each other using a variety of networks such an Internet Protocol (IP) network and a Synchronous Optical Network (SONET). SONET is the United States standard for synchronous data transmission on optical media. The international equivalent of SONET is synchronous digital hierarchy (SDH). Together, they ensure standards so that digital networks can interconnect internationally and that existing conventional transmission systems can take advantage of optical media.
Computer systems use network protocol related circuitry, such as network adapters, to encode and decode the data that is transmitted on a network for error detection and correction purposes. Selective byte removal and addition is commonplace in various protocol implementations and internet-working specifications. These two factors lead to the generation of arbitrary data streams, from a hitherto regular data stream, which have to be gathered and aligned for efficiency and ease of manipulation. The generation of regular data streams allows for efficient use of line bandwidth for faster data transmit times. In addition, regular data streams are easier to manipulate, more conducive to pipelining, and easier to fetch and store. These factors are accorded high importance in network circuits and systems since they impact the key differentiating parameters for customers and the marketplace.
One type of circuit that operates to map arbitrary data streams to a regular data stream is known as a data aligner. More specifically, a data aligner takes unaligned data in various byte sizes and aligns the data to achieve a packed byte size. One problem with some prior data aligners is that they contain an extensive amount of logic in the first of multiple stages of a design in order to deal with as many unaligned data scenarios as possible. Another problem with some prior data aligners is that they feedback the output of an output selection multiplexer to an intermediate buffer, thereby leading to congestion of logic in the first stage of a design. This is because such a solution, when it realizes that there is not enough data in certain packets to pass on as output, may tend to hold concatenated data in the intermediate buffer rather than run and restore the data. Such approaches may not only be difficult to design but may also result in higher processing times in the data aligner's first stage, thereby, limiting the frequency at which such data aligners may operate.
SUMMARY OF THE INVENTION
The present invention pertains to a method and apparatus for data alignment. The apparatus may include a plurality of circuitry stages coupled between a plurality of buffers. Later stage circuitry and corresponding buffers may be used to distribute the generation of an aligned data packet to reduce the operational time of earlier stage circuitry.
In one particular embodiment, the apparatus may include first stage circuitry coupled to a first buffer. The first stage circuitry may include a rotator coupled to the first buffer, a controller coupled to the rotator, and a first multiplexer coupled to the controller. The apparatus may also include a second buffer coupled to the rotator and second stage circuitry coupled to the second buffer. The second stage circuitry may include a second multiplexer. A third buffer may also be coupled to the second stage circuitry.
In one embodiment, the method may include receiving a first data element having a plurality of bytes and determining a first number of the plurality of bytes that contain data. The method may also include passing the first data element without operating on the first data element if all of the plurality of bytes that contain data and holding the data element if less than all of the plurality of bytes contain data.
In another embodiment, the method may include receiving a head element having empty byte positions out of a plurality of byte positions and receiving a first succeeding body element. The method may also include operating on the head element to generate a first packed element by combining the head element with the first succeeding body element to fill the empty byte positions of the head element with data from the first succeeding body element. The first packed element may have the plurality of byte positions. The method may also include transmitting the first packed element if the plurality of byte positions of the first packed element are filled by the operation.
In yet another embodiment, the method may include receiving a first number of bytes of a non-continuous data stream and passing the first number of bytes through first and second buffers to a third buffer. The first number of bytes may be less than a predetermined number of bytes. The first buffer may be coupled to the second buffer and the second buffer may be coupled to the third buffer. The method may also include receiving a second number of bytes and passing on the first number of bytes from the second buffer to the third buffer. The method may also include feeding back the third buffer to the second buffer if the sum of the first and second numbers of bytes is less than the predetermined number.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
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patent: 0502544 (19
Catamaran Communications Incorporated
Dicke Billig & Czaja, PLLC
Le Dieu-Minh
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