Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-02
2007-01-02
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10898574
ABSTRACT:
An approach for cut-point frontier selection and/or counter-example generation. Both a lazy and an eager cut-point frontier are identified. A reconvergence (or non-reconvergence) ratio is then computed for each of the frontiers and the one with the smaller (larger) reconvergence (non-reconvergence) ratio is selected as the next cut-point frontier. For another aspect, to generate a counter-example, in response to identifying a difference in output signals for a given cut-point frontier, values of eigenvariables and reconverging primary inputs are used to compute the corresponding values of the non-reconverging primary inputs. These corresponding values are then computed to be compatible with the internal signal values implied by the cut-point frontier selections that were made to expose the difference in the outputs.
REFERENCES:
patent: 5202889 (1993-04-01), Aharon et al.
patent: 5331568 (1994-07-01), Pixley
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5638381 (1997-06-01), Cho et al.
patent: 5724504 (1998-03-01), Aharon et al.
patent: 5748497 (1998-05-01), Scott et al.
patent: 5754454 (1998-05-01), Pixley et al.
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 5937183 (1999-08-01), Ashar et al.
patent: 6006028 (1999-12-01), Aharon et al.
patent: 6035107 (2000-03-01), Kuehlmann et al.
patent: 6035109 (2000-03-01), Ashar et al.
patent: 6086626 (2000-07-01), Jain et al.
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6212669 (2001-04-01), Jain
patent: 6269467 (2001-07-01), Chang et al.
patent: 6301687 (2001-10-01), Jain et al.
patent: 6308299 (2001-10-01), Burch et al.
patent: 6334205 (2001-12-01), Iyer et al.
patent: 6378112 (2002-04-01), Martin et al.
patent: 6408424 (2002-06-01), Mukherjee et al.
patent: 6449750 (2002-09-01), Tsuchiya
patent: 6470482 (2002-10-01), Rostoker et al.
patent: 6473884 (2002-10-01), Ganai et al.
patent: 6484135 (2002-11-01), Chin et al.
patent: 6564358 (2003-05-01), Moondanos et al.
patent: 2001/0025369 (2001-09-01), Chang et al.
patent: 2002/0073380 (2002-06-01), Cooke et al.
patent: 2002/0108093 (2002-08-01), Moondanos et al.
patent: 2002/0144215 (2002-10-01), Hoskote et al.
patent: 2003/0200073 (2003-10-01), Rich et al.
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, “Aquila: An Equivalence Verifier for Large Sequential Circuits”, Proceedings of Asia and South Pacific Design Automation Conference, Jan. 1997, pp. 455-460.
Paruthi et al., “Equivalence Checking Combing a Structural SAT-solver, BDDs, and Simulation”, Proceeding of the 2000 International Conference on Computer Design, pp. 459-464, Sep. 17, 2000.
Krohm et al., “The Use of Random Simulation in Formal Verification”, Proceedings of the 1996 IEEE International Conference on Computer Design: VSLI in Computers and Processors, pp. 371-376, Oct. 7, 1996.
Rho et al., “Inductive Verification of Iterative Systems”, Proceedings of the 29thACM/IEEE Design Automation Conference, pp. 628-633, Jun. 8, 1992.
C. Leonard Berman, Louise H. Trevillyan, “Functional Comparison of Logic Designs for VLSI Circuits”, 1989 IEEE, pp. 456-459.
Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato, “Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams”, 1988 IEEE, pp. 2-5.
Richard Rudell, “Dynamic Variable Ordering for Ordered Binary Decision Diagrams”, 1993 IEEE, pp. 42-47.
Andreas Kuehlmann, Florian Krohm, “Equivalence Checking Using Cuts and Heaps”, pp. 263-268, unavailable.
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell, Efficient Combinational Verification Using BDDs and a Hash Table, 1997 IEEE, Jun. 9-12, 1997, Hong Kong, pp. 1025-1028.
Elena Dubrova, Luca Macchiarulo, “A Comment on Graph-Based Algorithm for Boolean Function Manipulation”, 2000 IEEE, vol. 49, No. 11, Nov. 2000, pp. 1290-1292.
Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan, “Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment”, 1995 ACM 0-89791-756-1/95/0006, pp. 1-6.
Randal E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation12”, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA 15213, table of contents and pp. 1-25, unavailable.
Yusuke Matsunaga, “An Efficient Equivalence Checker for Combinational Circuits”, Fujitsu Laboratories Ltd., Kawasaki 211-88, Japan, 41.1, pp. 629-634, unavailable.
Corno et al., “Simulation-based Sequential Equivalence Checking of RTL VHDL”, Proceedings of the 1999 IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 351-354, Sep. 5, 1999.
Hanna Ziyad E.
Khasidashvili Zurab
Moondanos John
Chiang Jack
Foatz Cynthia Thomas
Tat Binh
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