Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-24
2005-05-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000, C716S030000, C716S030000
Reexamination Certificate
active
06898767
ABSTRACT:
Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.
REFERENCES:
patent: 5222030 (2002-10-01), Rostoker et al.
patent: 6470482 (2002-10-01), Rostoker et al.
Do Thuan
LSI Logic Corporation
Siek Vuthe
The Law Offices of William W. Cochran, LLC
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