Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-21
2002-02-26
Bowers, Charles (Department: 2813)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06351841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of integrated circuit compactors, and more particularly, to a method and apparatus for creating multi-gate transistors that are compatible with integrated circuit polygon compactors.
2. Description of the Related Art
As semiconductor manufacturing technology allows ever smaller feature sizes each year, many existing designs are modified to take advantage of the increased speed and density afforded by the new processes. The layout rules for a new technology are seldom the result of simply scaling the old rules. Usually the minimum widths, spaces and overlaps are reduced by different amounts. The process of modifying an integrated circuit layout to conform to a new set of layout rules is known as migration. For small designs, migration by manual re-layout may be acceptable. For larger designs of several million transistors, however, a tool called a compactor, such as Dream™ from Sagantec, is used. Dream™ stands for Design Rule Enforcement and Migration. A compactor reads the new design rules and moves the edges of the polygons representing the features on each layer of the old layout to force compliance with the new rules. A compactor simply recognizes shapes (edges) and adjusts the relative sizes of corresponding polygons, but does not change the number of polygons. In other words, a compactor does not add any, new structure and therefore the resulting new layout has the same number of polygons as the original layout.
After a design has been migrated to a new process, it is oftentimes desirable to optimize the speed and reduce the power of the design by tuning transistor sizes with a tool such as Virtuoso Core Optimizer™ from Cadence or AMPS™ from Synopsis. Having determined the desired sizes of the transistors, a compactor can then be used to change the transistor sizes. The desired transistors are re-sized by the compactor in accordance with a list of sizes, names and/or locations of the transistors. In order to provide additional space for the larger transistors, the compactor also adjusts the features of the surrounding areas to be as tightly packed as possible without violating the design rules.
In order to meet the timing requirements, many transistor sizes may increase in size several times, as shown in FIG.
1
. Each transistor
10
,
12
consists of a diffusion region
14
, a polysilicon layer
16
, and contacts
181
,
182
. Note that the “large” transistor
12
is much longer than the “small” transistor
10
, and normally includes extra contacts
183
-
186
. One of the biggest limitations of the standard polygon layout compactor is that when transistor sizes need to be increased significantly (i.e., several times) in order to meet the timing requirements, the enlarged transistors may extend well beyond the compact group to which they belong. Since transistors cannot overlap adjacent regions, the adjacent regions have to be moved to make space for the enlarged transistors. This causes wasteful and unsightly gaps in the layout, which reduces the density.
For manual custom designs, the solution is to construct a multi-gate transistor to replace the single large gate transistor. A multi-gate transistor, illustrated in FIG.
2
(
a
), is actually a compact set of smaller transistors sharing common source
22
and drain
24
areas, and having connected gates
20
. The smaller transistors are connected so that they are electrically in parallel (as illustrated by the equivalent circuit of FIG.
2
(
b
)), and thus act as a single transistor of the same effective size as the original larger one. A multi-gate transistor can be formed to be roughly square, thus producing a compact design. The single large equivalent transistor would be much longer, and much more difficult to efficiently place in the layout.
The basic compactor algorithms, however, cannot perform this process, since the compactor only moves polygon edges. In other words, prior art compactors are not capable of creating new structures (other than arrays of contacts).
SUMMARY OF THE INVENTION
In general, the present invention is a method and apparatus for creating multi-gate transistors with integrated circuit polygon compactors. More particularly, in order to provide a more efficient layout when the size of a transistor is increased during design migration, a small multi-gate transistor is formed by inserting at least one parallel “narrow” transistor over the diffusion layer of a target transistor, between a gate and contact. The compactor then enforces the new design rules, and adjusts the relative sizes of the parallel transistors as required. The resulting multi-gate transistor structure is much more compact than a single large transistor, providing a more efficient design layout.
Thus, the present invention makes it practical to use a polygon compactor for making significant changes in transistor sizes, such as required when optimizing the speed of a circuit. Without the present invention, the layout would become distorted and have lower density. The present invention applies generally to polygon compactors capable of changing the sizes of transistors in a layout using sizing information stored in a data file, and that enforce compliance with the design (layout) rules in a space conserving manner. These and other aspects of the invention, as well as further details of specific embodiments, may be more fully understood from the following specification and drawings.
REFERENCES:
patent: 5535134 (1996-07-01), Cohn et al.
patent: 5604680 (1997-02-01), Bamji et al.
patent: 5610831 (1997-03-01), Matsumoto
patent: 5612893 (1997-03-01), Hao et al.
patent: 5634093 (1997-05-01), Ashida et al.
patent: 5675501 (1997-10-01), Aoki
patent: 5974244 (1999-10-01), Hayashi et al.
patent: 6031980 (2000-02-01), Oota
patent: 6163877 (2000-12-01), Gupta
patent: 6209119 (2001-03-01), Fukui
Sagantec Web Page, http://www.sagantec.com/dream-applications.html, no date.
Sagantec Web Page, http://sagantec.com/features.html, no date.
Virtuoso Compactor Datasheet (Web Page Version) 1997, Cadence Design Systems, Inc. Marketing Services.
Cadence Design Systems Inc.
Crosby, Heafey Roach & May
Kielin Erik J.
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