Electronic digital logic circuitry – Reliability – Redundant
Reexamination Certificate
2005-11-08
2005-11-08
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Reliability
Redundant
C326S038000
Reexamination Certificate
active
06963217
ABSTRACT:
A method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified.
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Katkoori Srinivas
Ramos Jeremy
Samudrala Praveen K.
Chang Daniel
Honeywell Space Systems, Inc.
Sauter Molly L.
Smith & Hopen , P.A.
University of South Florida
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