Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-05
2004-08-17
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S363000, C257S357000, C257S358000, C257S533000, C257S537000
Reexamination Certificate
active
06777755
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention generally relates to integrated circuits (ICs) and, more particularly, to a method and apparatus for creating a reliable long resistor/capacitor (RC) time constant in order to reduce the possibility of electrostatic discharge (ESD) core shunts being turned on in the IC when they shouldn't be.
BACKGROUND OF THE INVENTION
One well known use for creating long RC time constants is in ESD structures, which are used to shunt static electricity from power supplies (VDD) in an IC to ground. As is commonly known in the art, static electricity can build up on VDD nodes within an IC due to various causes, such as when a person handling the IC touches a pin of the IC. This is one type of ESD event that causes a VDD node to begin charging up, and this charge needs to be shunted to ground to prevent damage to the IC. The manner in which an ESD event is commonly handled can be seen in FIG.
1
.
FIG. 1
illustrates a schematic diagram of a typical ESD structure
1
. During an ESD event, the VDD node
2
begins being charged and the power supply begins to rise. The SHUNTN signal remains constant due to the high RC time constant of the resistor
3
/capacitor
4
combination. When VDD rises to a high enough level, it will begin to turn on the PFET, p
1
, labeled with the numeral
5
. This, in turn, will charge up the gate node
6
, which will turn on a relatively large NFET, n
2
, labeled with the numeral
7
. The NFET n
2
7
is designed to shunt large amounts of current between VDD and ground, GND. This provides an ESD path from VDD to GND during an ESD event, thereby preventing elements in the IC from being damaged due to high voltages caused by the build up of electrostatic charges.
In current ESD structure designs, it is known to use either a poly, active, or nwell resistor in combination with a diode to create the RC combination represented by the resistor
3
/capacitor
4
combination shown in FIG.
1
. The problem with such an ESD structure is that, because of the large RC time constant needed (e.g., >300 nanoseconds (ns)), this design may allow charge to leak off of the SHUNTN node
8
. The charge on the SHUNTN node needs to remain relatively stable to ensure that the RC time constant is longer than an ESD event. Otherwise, the ESD structure will not operate properly, i.e., the gate node
6
will not charge up and turn on NFET n
2
7
, and the charge on VDD will not be shunted from VDD through NFET n
2
7
to GND.
Accordingly, a need exists for an ESD structure with a reliable long RC time constant. By ensuring that the RC time constant is reliable, any potential damage to elements of the IC due to high voltage levels caused by electrostatic charge build up can be prevented.
SUMMARY OF THE INVENTION
In accordance with the present invention, an electrostatic discharge (ESD) structure is provided for use in an integrated circuit (IC). The ESD structure comprises a metallic resistor and a metallic capacitor that are electrically coupled in series to form a resistor-capacitor (RC) component having an appropriate RC time constant. The RC component maintains a level of charge between the shunt node and ground to ensure that, during an ESD event, electrostatic charge on the power supply VDD is shunted via a shunt path from said power supply VDD to said ground. By using metal to create the metal resistor and capacitor, charge leakage problems due to parasitic capacitance associated with an RC component comprised of either a poly, active, or nwell resistor in combination with a diode are eliminated. The problem with such an ESD structure is that, because of the large RC time constant needed, this design may allow charge to leak off of the SHUNTN node. By using metal to create the metal resistor and capacitor, such charge leakage problems caused by parasitic capacitance are eliminated, which results in a more reliable RC component and thus a more reliable RC time constant.
REFERENCES:
patent: 5535086 (1996-07-01), Mentzer
patent: 5789694 (1998-08-01), Mey
patent: 6046894 (2000-04-01), Ida
patent: 2003/0058061 (2003-03-01), Shih et al.
Dondale C. Stephen
Gonzalez Jason
Humphrey Guy Harlan
Krzyzlowski Richard A
Agilent Technologie,s Inc.
Tran Minhloan
Tran Tan
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