Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-12-31
2004-11-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000
Reexamination Certificate
active
06823503
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention relates to the process of fabricating integrated circuits. More specifically, the invention relates to a method and an apparatus for creating a phase-shifting mask for a photolithographic process used in fabricating integrated circuits.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photoresist layer. (Note that the term “mask” as used in this specification is meant to include the term “reticle.”) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some type of electromagnetic radiation source together with suitably adapted masks and lithography equipment.
This image is reduced and focused through an optical system containing a number of lenses, filters, and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, opaque regions of the mask block the light leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
As integration densities continue to increase, it is becoming necessary to use phase shifters to define more and more features within a layout. However, as phase shifters are used to define more features within a layout, it is becoming increasingly common for phase conflicts to occur between the shifters. Note that a pair of phase shifters used to create a critical dimension feature are generally required to have opposite phase. It is hard to satisfy this constraint if critical dimension features are packed so closely together so that their respective phase shifters merge or overlap.
The problem of assigning phases to phase shifters is generally solved by first placing the phase shifters on the phase shifting mask, and then attempting to “color” the phase shifters with two colors, a first color for zero-degree phase shifters, and a second color for 180-degree phase shifter. The coloring process is successful if all of the phase shifters can be colored without creating conflicts between adjacent phase shifters. Otherwise, if the coloring process is not successful, the layout is modified and/or the phase shifters are modified and the coloring process is repeated. This coloring process and the associated modifications to the layout and/or the phase shifters is an extremely time-consuming process.
What is needed is a method and an apparatus for generating a phase-shifting mask without the problems described above.
SUMMARY
One embodiment of the invention provides a system that creates a phase-shifting mask for a photolithographic process used in fabricating an integrated circuit. The system starts by receiving a layout for the integrated circuit. The system then associates nodes with features in the layout, and generates arcs between the nodes. Next, the system generates a coloring for the nodes using two colors. The system then generates phase shifters for the phase-shifting mask and assigns different phases to the phase shifters based upon the coloring of the nodes.
In a variation of this embodiment, generating arcs between the nodes involves using a first type of arc and a second type of arc, and coloring the nodes involves ensuring that nodes connected by the first type of arc have the same color and that nodes connected by the second type of arc have a different color.
In a variation of this embodiment, associating nodes with features in the layout involves associating nodes with white spaces in the layout so that a graph created by adding arcs between the nodes is planar.
In a variation of this embodiment, generating arcs between the nodes involves assigning weights to arcs based upon the sizes and geometries of features associated with the nodes.
In a further variation, associating nodes with features in the layout involves: decomposing the layout into a plurality of edges, and creating zero or more nodes for each edge in the plurality of edges.
In a variation of this embodiment, creating zero or more nodes for each edge of the plurality of edges involves: creating zero nodes for feature ends; creating two nodes for a T-joint edge; and creating one node for remaining edges.
In a variation of this embodiment, the two colors include a first color that corresponds with a zero-degree phase shifter on the phase-shifting mask, and a second color that corresponds with a 180-degree phase shifter on the phase-shifting mask.
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Publication entitled “Subwavelength Optical Lithography: Challeges and Impact on Physical Design,” by A.B. Kahng et al., proceedings of 1999 International Symposium on Physical Design, Monterey, CA, Apr. 12-14, 1999.
Numerical Technologies Inc.
Park, Vaughan & Fleming
Siek Vuthe
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