Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-11-22
2002-04-02
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
06366991
ABSTRACT:
TECHNICAL FIELD
This invention relates to coupling signals from one electronic device to another, and more particularly to coupling signals between electronic devices having different clock domains defined by respective clocks that may differ from each other.
BACKGROUND OF THE INVENTION
Many electronic devices operate in a synchronous manner in which the timing of signals in the device are controlled by a clock signal. The transitions of the clock signal occur at substantially the same time throughout the circuit, thereby ensuring that signals coupled or created responsive to the transitions of the clock signal are properly synchronized to each other.
Although synchronism between signals can be maintained when the same clock signal, or clock signals derived from the same clock signal, are used throughout a circuit. It is substantially more difficult to properly synchronize signals coupled from one electronic device to another when the electronic devices operate in different clock domains defined by different clock signals.
With reference to
FIG. 1. a
first electronic device
10
receives a signal S
i
and a clock signal CLKA. The electronic device outputs a signal S
2
responsive to the input signal S
i
and transitions of the clock signal CLKA. The signal S
2
is coupled to the input of a second electronic device
12
through a line
14
. The second electronic device
12
also receives a second clock signal CLKB. The second clock signal CLKB may have a phase that is different from the phase of the first clock signal CLKA, and it may even have a frequency that is different from the frequency of the first clock signal CLKA. The problem encountered when coupling the signal S
2
from the output of the first device
10
to the input of the second device
12
is illustrated in FIG.
2
.
The clock signal CLKA for the first electronic device
10
is shown in
FIG. 2A
, and the input signal S
i
is shown in
FIG. 2B
as going high at time t
0
. By way of example, the first electronic device
10
simply performs a logical AND function of the input signal S
i
and the clock signal CLKA to generate the signal S
2
. The signal S
2
is shown in
FIG. 2C
with exponentially rising and falling edges because of the capacitive loading on the line
14
coupling the first electronic device
10
to the second electronic device
12
.
An example of a clock signal CLKB
1
having a first phase is illustrated in FIG.
2
D. As shown by comparing
FIG. 2A
with
FIG. 2D
, the clock signal CLKA for the first electronic device
10
lags the clock signal CLKB
1
for the second electronic device
12
. By way of example, it is assumed that the second electronic device
14
simply functions to clock the signal S
2
(
FIG. 2C
) on either the rising edge of the clock signal CLKB
1
(
FIG. 2F
) or the falling edge of the clock signal CLKB
1
(FIG.
2
G). As shown in
FIG. 2F
, the second electronic device
12
is incapable of detecting the signal S
2
when the device
12
is clocked on the rising edge of CLKB
1
because the signal S
2
is not present at the input to the electronic device
12
on the rising edge of CLKB
1
. However, as shown in
FIG. 2G
, the second electronic device
14
is able to detect the signal S
2
if the electronic device
12
clocks the signal S
2
on the falling edge of the clock signal CLKB
1
. Thus, the second electronic device
12
can function with the first electronic device
10
despite having different clock domains, but only as long as the clock signal CLKB
1
leads the clock signal CLKA. If the electronic device
12
clocks the signal S
2
on the falling edge of CLKB
1
, it will not be able to detect the signal S
2
if the clock signal CLKB lags the clock signal CLKA.
An example of a clock signal CLKB
2
that lags the clock signal CLKA is illustrated in FIG.
2
E. The first clock signal CLKA is considered to lag the second clock signal CLKB if any transition of the first clock signal CLKA occurs more than 0 degrees and less than 180 degrees after the corresponding transition of the second clock signal CLKB. The first clock signal CLKA is considered to leasd the second clock signal CLKB if any transition of the first clock signal CLKA occurs more than 180 degrees and less than 0 degrees after the corresponding transition of the second clock signal CLKB. Again. it is first assumed that the second electronic device
12
functions to clock the signal S
2
on the rising edge of the clock signal CLKB
2
(
FIG. 2H
) or the falling edge of the clock signal CLKB
2
(FIG.
2
I). As shown in
FIG. 2H
, the second electronic device
12
is able to detect the signal S
2
if the electronic device
12
clocks the signal S
2
on the rising edge of the clock signal CLKB
2
. However, as shown in FIG.
2
I. the second electronic device
12
is incapable of detecting the signal S
2
if the electronic device
12
clocks the signal on the falling edge of the clock signal CLKB
2
because the signal S
2
is not present at the input to the electronic device
12
on the falling edge of the clock signal CLKB
2
.
It will be apparent from the above discussion that the second electronic device
12
is able to detect the signal S
2
generated by the first electronic device
10
as long as either the second clock signal CLKB leads the first clock signal CLKA and the second electronic device
12
clocks the signal S
2
on the falling edge of CLKB, or the second clock signal CLKB lags the first clock signal and the second electronic device
12
clocks the signal S
2
on the rising edge of CLKB. However, because the first and second electronic devices
10
,
12
, respectively, are operating in different clock domains, the phase relationship between CLKA and CLKB can change. Therefore, if the choice is made to make the second electronic device
12
clock the signal S
2
on the falling edge of CLKB. it is possible for the clock signal CLKB to lag the first clock signal CLKA. As explained above, the second electronic device
12
will be unable to detect the signal S
2
under these conditions. Similarly, if the choice is made for the second electronic device
12
to clock the signal S
2
on the rising edge of CLKB, it is possible for the clock signal CLKB to lead the first clock signal CLKA. Again. the second electronic device
12
will be unable to detect the signal S
2
.
A more concrete example of the problem illustrated
FIGS. 1 and 2
is exemplified by a memory device
20
shown in FIG.
3
. The memory device
20
illustrated in
FIG. 3
is a packetized dynamic random access memory (“DRAM”) having an architecture known as SyncLink. However, the problem may also exist to varying degrees with other types of memory devices, such as synchronous DRAMs. The packetized memory device
20
is shown in somewhat generalized form because the specific structure of the memory device
20
is somewhat peripheral to the inventions described herein. However, packetized memory devices
20
are explained in greater detail in the U.S. patent applications Ser. Nos. 08/877,191 and 08/874,690.626 to Troy A. Manning which are incorporated herein by reference.
The memory device
20
includes a controller
22
that receives a command packet CA, generally containing several multi-bit packet words, a flag signal F indicating the start are a command packet, and a command clock CMDCLK synchronized to the packet words. The command packet CA includes both memory commands, such as read, write, etc., and bank, row and column address information, as well as other information used to initialize or operate the memory device
20
.
The memory device
20
also includes a clock generator
24
that receives the command clock CMDCLK as well as control signals from the controller
22
. The clock generator
24
produces several clock signals from the command clock CMDCLK, including an internal clock signal ICLK and a read clock signal RCLK. The phase of the internal clock signal ICLK and the phase of the read clock signal RCLK are determined by control signals from the controller
22
. The controller
22
uses the internal clock signal ICLK to generate a
Dorsey & Whitney LLP
Ellis Kevin L.
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