Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1997-02-18
1999-11-16
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
H04L 700, H04L 2536, H04L 2540
Patent
active
059870842
ABSTRACT:
The output phase measures output by a digital phase lock loop (DPLL) are selectively modified to reduce instantaneous phase errors incurred whilst waiting until the DPLL locks before obtaining an accurate phase measurement of a signal. In one embodiment, the output phase of a low bandwidth DPLL is selectively modified when the input signal exhibits a significant dynamic transient by adding the error term generated by the DPLL phase detector to the output signal generated by the DPLL to generate a modified output signal used to perform phase measurements.
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Chin Stephen
Ghayour Mohammad
Trimble Navigation Limited
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