Method and apparatus for correcting duty cycle via current...

Details Method and apparatus for correcting duty cycle via current... Method and apparatus for correcting duty cycle via current...

2011-05-03

2011-05-03

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

Reexamination Certificate

active

07936186

ABSTRACT:
Embodiments of the invention relate generally to the field of duty cycle correction, and more particularly to method and apparatus for correcting duty cycle of a CMOS level signal when converted from a Current-Mode-Logic (CML) to a CMOS level signal via a CML to CMOS converter. The converter comprises a first differential pair unit to receive a CML level signal; a second differential pair unit to receive the CML level signal; and an embedded differential biasing unit, coupled with the first and the second differential pair units, to adjust drive strength of the first and second differential pair units based on a duty cycle of the CML level signal. The method for correcting duty cycle of the CMOS level signal output comprises receiving by the first differential pair unit a CML level signal; receiving by the second differential pair unit the CML level signal; and adjusting drive strength of the first and the second differential pair units based on a duty cycle of the CMOS level signal.

REFERENCES:
patent: 6211699 (2001-04-01), Sudjian
patent: 2008/0001633 (2008-01-01), Narathong et al.
patent: 2009/0284288 (2009-11-01), Zhang et al.
Wang, Huaide, et al., “A 21-Gb/s 87-m Transceiver with FFE/DFE/Linear Equalizer in 65-mn CMOS Technology”, Symposium on VLSI Circuits Digest of Technical Papers, 2009, (2009) pp. 50-51.

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