Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-14
2007-08-14
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10904397
ABSTRACT:
A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.
REFERENCES:
patent: 4544914 (1985-10-01), Chan et al.
patent: 5379327 (1995-01-01), Sharma et al.
patent: 5418930 (1995-05-01), Swarts
patent: 5606564 (1997-02-01), Ho et al.
patent: 6088821 (2000-07-01), Moriguchi et al.
patent: 6140946 (2000-10-01), Desrosiers et al.
patent: 6339338 (2002-01-01), Eldridge et al.
patent: 6445065 (2002-09-01), Gheewala et al.
patent: 6456103 (2002-09-01), Eldridge et al.
patent: 6550045 (2003-04-01), Lu et al.
patent: 2004/0015790 (2004-01-01), Cunningham et al.
patent: 2004/0153980 (2004-08-01), Wilcox et al.
patent: 2004/0153981 (2004-08-01), Wilcox et al.
patent: 2005/0102643 (2005-05-01), Hou et al.
patent: 2005/0198601 (2005-09-01), Kuang et al.
patent: 2006/0190899 (2006-08-01), Migatz et al.
patent: WO 99/62173 (1999-12-01), None
Haar Allen P.
Iadanza Joseph A.
Ventrone Sebastian T.
Wemple Ivan L.
Chiang Jack
Dillon & Yudell LLP
Dimyan Magid Y.
Harding Riyan
LandOfFree
Method and apparatus for converting globally clock-gated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for converting globally clock-gated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for converting globally clock-gated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3827591