Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-10-27
2001-11-20
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S100000, C711S111000, C711S112000, C711S154000
Reexamination Certificate
active
06321294
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to Redundant Array of Independent Disks (RAID) systems, and in particular to methods for efficiently allocating memory space in RAID systems allowing different configurations.
RAID systems allow the storing of memory data across multiple disks. A number of different levels of RAID are available, ranging from mirroring of disks to more complicated striping configurations across larger groups of disks with error correction and redundancy data. The number of disks in a redundancy group can vary from two to three to four to five to any other number. In some environments, such as network environments, multiple users may be using the same physical disk drives, but may use different levels of RAID for storing their particular data.
Accordingly, one of the challenges in the RAID system is to efficiently and consistently translate between logical memory space and physical memory space on the disk drives or other memory device in accordance with the different RAID parameters of different blocks of data. Two types of transformations are generally needed. First, a logical to physical transformation needs to transform the data requests from the logical address space to physical accesses on individual members, disk drives, or memory devices in the RAID redundancy group. Second, a conversion from a physical address on a device in the redundancy group to a logical address on the array is required during certain types of operations.
The conversion or translation calculations are different for each RAID type and configuration. For example, a 2-wide RAID array using mirror redundancy uses one set of conversion algorithms while another array configured for 9 drives and parity type redundancy uses a completely different type of conversion and thus a different set of algorithms must be generated. The type of redundancy used (sometimes called the “RAID level”), the width of the array, the striping factor, and other elements of the array's configuration all require modifications to the algorithms of translation. Obviously, this makes the programming more complex and subject to error.
SUMMARY OF THE INVENTION
The present invention provides a method for converting between logical and physical memory space which adapts to different RAID types and configurations in a modular form. In particular, a module containing a standard set of conversion algorithms is used for all conversions. The standard set of conversion or translation algorithms operate on a pseudo representation of a RAID array that has all redundant components removed. For each RAID type and configuration, the standard algorithms can be used unchanged if a method is provided to convert the real RAID array representation into the pseudo version and back again. This simplifies both the programming and the debugging. This also makes the software more modular and more easily upgradeable.
In one embodiment, the primary transformation creates a pseudo stripe from a number of real stripes which differs from the redundancy groupings. Preferably, this is done by selecting a number of real stripes which will end on the boundary of a redundancy grouping.
In one embodiment, conversion uses a value calculated by dividing the redundancy group width by the greatest common factor of the redundancy group width and the physical array width. The whole number portion of the result then provides the number of real physical stripes in a single pseudo stripe. This value is essential to conversion between the real and pseudo representation of this type of array and back again. During translation from logical to physical address spaces as described above, the real array representation is converted with the help of this value to the pseudo representation at which time the, standard translation algorithms can be applied. Subsequently, the output of the standard algorithms using the pseudo representation is converted using this value to values that apply to the real array representation which can then be used for access to the actual devices of the array.
In one embodiment, upon creation of the array, the pseudo to real conversion factor is determined and stored so that it need not be recalculated for each operation.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5613085 (1997-03-01), Lee et al.
patent: 5758118 (1998-05-01), Choy et al.
patent: 5948110 (1999-09-01), Hitz et al.
patent: 5974515 (1999-10-01), Bachmat et al.
patent: 6151641 (2000-11-01), Herbert
MTI Technology Corporation
Thai Tuan V.
Townsend and Townsend / and Crew LLP
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