Method and apparatus for controlling the writing and erasing of

Details Method and apparatus for controlling the writing and erasing of Method and apparatus for controlling the writing and erasing of

1994-08-19

1998-09-01

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

G06F 1300

Patent

active

058025510

ABSTRACT:
Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

REFERENCES:
patent: 5341339 (1994-08-01), Wells
patent: 5357475 (1994-10-01), Hasbun et al.
patent: 5437020 (1995-07-01), Wells et al.
patent: 5459850 (1995-10-01), Clay et al.
patent: 5473753 (1995-12-01), Wells et al.
patent: 5479633 (1995-12-01), Wells et al.

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