Method and apparatus for controlling the processing priority...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

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C712S228000

Reexamination Certificate

active

06928647

ABSTRACT:
The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thread. In one embodiment, the processing priority is initially assigned to the first thread for a first duration. It is then determined whether the first duration has expired in a given processing cycle. If the first duration has expired, the processing priority is assigned to the second thread for a second duration.

REFERENCES:
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 5357617 (1994-10-01), Davis et al.
patent: 5386561 (1995-01-01), Huynh et al.
patent: 5404469 (1995-04-01), Chung et al.
patent: 5430850 (1995-07-01), Papadopoulos et al.
patent: 5499349 (1996-03-01), Nikhil et al.
patent: 5524263 (1996-06-01), Griffth et al.
patent: 5791522 (1998-08-01), Lee et al.
patent: 5809271 (1998-09-01), Colwell et al.
patent: 5809522 (1998-09-01), Novak
patent: 5892959 (1999-04-01), Fung
patent: 5900025 (1999-05-01), Sollars
patent: 5968160 (1999-10-01), Saito et al.
patent: 5968167 (1999-10-01), Whittaker et al.
patent: 5996085 (1999-11-01), Cheong et al.
patent: 5999932 (1999-12-01), Paul
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6052709 (2000-04-01), Paul
patent: 6088788 (2000-07-01), Borkenhagen et al.
patent: 6092175 (2000-07-01), Levy et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6115709 (2000-09-01), Gilmour et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6233599 (2001-05-01), Nation et al.
patent: 6256775 (2001-07-01), Flynn et al.
patent: 6389449 (2002-05-01), Nemirovsky et al.
patent: 6430593 (2002-08-01), Lindsley
patent: 6542921 (2003-04-01), Sager
patent: 0346003 (1989-06-01), None
patent: 346003 (1989-06-01), None
patent: 0352935 (1989-07-01), None
patent: 352935 (1989-07-01), None
patent: 0725335 (1996-01-01), None
patent: 725335 (1996-01-01), None
patent: 747816 (1996-05-01), None
patent: 0747816 (1996-05-01), None
patent: 0768608 (1997-04-01), None
patent: 0768608 (1997-04-01), None
patent: 0768608 (1997-04-01), None
patent: 0827071 (1997-08-01), None
patent: 827071 (1997-08-01), None
patent: 0856797 (1998-05-01), None
patent: 0856797 (1998-05-01), None
patent: 962586 (1999-05-01), None
patent: 0962856 (1999-05-01), None
patent: 2311880 (1996-03-01), None
patent: 2311880 (1996-03-01), None
patent: WO 99/21082 (1999-04-01), None
patent: WO 99/21088 (1999-04-01), None
patent: WO 99/21089 (1999-04-01), None
“Multithreading for Rookies”, Ruediger R. Asche, http://www.microsoft.com/win32dev/base/threads.htm, Jul. 31, 1998.
Simon W. Moore, Multithreaded Processor Design, Kluwer Academic Publishers, 1996.
Steere D C, et al., “A feedback-driven proportion allocator for real-rate scheduling” Third Symposium on Operating Systems Design and Implementation, New Orleans, LA USA, Feb. 22-25, 1999, pp 145-158, XP002153159, Operating Systems Review, Winter 1998, ACM USA ISSN: 0163-5980.
INTEL: “P6 Family of Processors—Chapters 1&2”, Hardware Developer's Manual, 'Online!, Sep. 1998, XP002153160, Retrieved from the Internet Nov. 16, 2000.
“Improved Dispatching in a Rendering Context Manager”, IBM Technical Disclosure Bulletin, US, IBM Corp., New York, vol. 33, No. 7, Dec. 1, 1990, pp 131-134, XP000108363 ISSN: 0018-8689.
Dongwook Kim, Joonwon Lee, Seungkyu Park, A Partitioned On-Chip Virtual Cache for Fast Processors, Journal of Systems Architecture 43, 1997, pp 519-531, Elsevier, South Korea.
Avi Mendelson, et al., Design Alternatives of Multithreaded Architecture, International Jounal of Parallel Programming, vol. 27, No. 3, 1999, pp 161-193, Plenum Publishing Corp.
“Architectureal and Implementation Tradeoffs in the Design of Multiple-Context Processors”, James Laudon, Anoop Gupta and Mark Horowitz, Multithread Computer Architecture: A Summary of the State of the Art, Chapter 8, pp. 167-200, Kluwer Academic Publishers 1994.
“Exploiting Choice: Instruction Fetch and Issue on an Implementaable Simultaneous Multithreading Processor”, Dan M. Tullsen, Susan J. Eggers, Joel S. Emerg, Henry M. Levy, Jack L. Lo and Rebecca L. Stammm, Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp. 191-202.
“Evaluation of Multithreaded Uniprocessors for Commercial Application on Environments”, Richard J. Eickemyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante and Shiafun Liu, Proceedings of the 23rd Annual International Symposium on Computer Architecture May 22-24, 1996, pp. 203-212.
“Performance Study of a Multithreaded Superscalar Microprocessor”, Manu Gulati and Nadar Bagherzadeh, Proccedings Second International Microprocessor, Manu Gulati and Nader Bagherzadeh, Proccedings Secon International Symposium on High-Performance Computer Architecture, Feb. 3-7, 1996, pp 291-301.
“A Benchmark Evaluation of a Multi-Threaded RISC Processor Architecture”, R. Guru Prasadh and Chuan-lin Wu, 1991 International Conference on Parallel Processing, pp I-81-I-191.
“Multithreading Comes of Age”, Peter Song, Microdesign Resources, Jul. 14, 1997, pp 13-18.
“Instruction Cache Fetch Policies for Speculative Execution”, Dennis Lee, Jean-Loup Baer, Brad Calder and Dirk Grunwald, 22nd International Symposium on Computer Architecture, Jun. 1995.
Matthew K. Farrens, et al., Proceedings the 18th Annual International Symposium on Computer Architecture, May 27-30, 1991, pp 362-369, Toronto Canada.
Steere D.C. et al., “A Feedback-Driven Proportions Allocator For Real-Rate Scheduling” Third Symposium on Operating Systems Design and Implementation, New Orleans, LA, USA, Feb. 22-25, 1999, pp 145-158, XP002153159, Operating Systems Review, Winter 1998, ACM, USA ISSN: 0163-5980.
INTEL “P6 Family of Processors—Chapters 1 & 2”, Hardware Developer's Manual, 'Online!, Sep. 1998, XP002153160, Retrieved from the Internet Nov. 16, 2000.
Dongwook Kim, Joonwon Lee, Seungkyu Park, A Partitioned On-Chip Virtual Cache For Fast Processors, Journal of System Architecture 43, 1997, pp 519-531, Elsevier, South Korea.
Matthew K. Farrens, et al., Proceedings The 19th Annual International Symposium on computer Architecture, May 27-30, 1991, pp 362-369, Toronto Canada.
James Laudon, Anoop Gupta & Mark Horowitz, “Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors”, Multithreaded Computer Architecture: A Summary of the State of the art, Chapter 8, pp 167-200, Kluwer Academic Publishers 1994.
Dan M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jadck L. Lo and Rebecca L. Stammm, Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor:, Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp 191-202.
Ricahrd J. Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Marks S. Squillante & Shiafun Liu, “Evaluations of Multithreaded Uniprocessors for Commercial Application Environments”, Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp 203-212.
Manu Gulati & Nader Bagherzadeh, “Performance Study of A Multithreaded Superscalar Microprocessor”, Proceedings Second International Symposium on High-Performance Computer Architecture, Feb. 3-7, 1996, pp 291-301.
Peter Song, “Multithreading Comes of Age”, Microdesign Resources, Jul. 14, 1997, pp 13-18.
R. Guru Prasadh & Chuan-Lin Wu, “A Benchmark Evaluation of a Multi-Threaded RISC Processor Architecture”, 1991 International Conference on Parallel Processing, pp I-84-I-91.
Dennis Lee, Jean-Joup Baer, Brad Clader & Dick Grunwald, “Instruction Cache Fetch Policies for Speculative Execution”, 22nd International Symposium on Computer Architecture, Jun. 1995.
Ruediger R. As

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