Method and apparatus for controlling the phase of the clock...

Details Method and apparatus for controlling the phase of the clock... Method and apparatus for controlling the phase of the clock...

2005-07-12

2005-07-12

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S503000, C713S400000

Reexamination Certificate

active

06918049

ABSTRACT:
A clock synthesizer produces an output clock that has a programmable phase offset from the input clock. The clock synthesizer includes an accumulator and an offset adder. The output clock is derived from the offset adder. The offset adder receives a value derived from the accumulator and a selected phase offset value. The phase difference between the non-aligned output clock and the aligned output clock is determined by the phase offset value. The time resolution of the clock synthesizer may be defined by the clock rate of the system and the number of bits used in the offset adder and the accumulator.

REFERENCES:
patent: 5687202 (1997-11-01), Eitrheim
patent: 5940608 (1999-08-01), Manning
patent: 6677786 (2004-01-01), Kellgren et al.

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