Method and apparatus for controlling the partial reconfiguration

Details Method and apparatus for controlling the partial reconfiguration Method and apparatus for controlling the partial reconfiguration

1997-12-12

2000-04-04

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, 326 41, 326 47, H03K 19177, H03K 19173

Patent

active

060466030

ABSTRACT:
A field programmable gate array (FPGA) having an array of configurable logic blocks (CLBs) which can be partially reconfigured. Each column of CLBs is connected to a corresponding column select line, and each row of CLBs is connected to a corresponding row select line. A rectangular set of CLBs to be reconfigured is selected, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs. Column select signals are asserted on the column select lines associated with the one or more consecutive columns of CLBs. Similarly, row select signals are asserted on the row select lines associated with the one or more consecutive rows of CLBs. CLBs which receive both an asserted column select signal and an asserted row select signal are enabled for reconfiguration.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5473267 (1995-12-01), Stansfield
patent: 5488582 (1996-01-01), Camarota
patent: 5600263 (1997-02-01), Trimberger et al.
"The Programmable Logic Data Book", (1996), available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 4-21 through 4-23.
"The Programmable Logic Data Book", (1994), available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, pp. 2-20 though 2-21.

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