Method and apparatus for controlling supply of power, and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S022000

Reexamination Certificate

active

06691248

ABSTRACT:

This application claims the benefit of a Japanese Patent Application No.11-361526 filed Dec. 20, 1999, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods and apparatuses for controlling supply of power and storage media, and more particularly to a power supply control apparatus and a power supply control method which control the supply of power to a computer system via an uninterrupted power supply (UPS), and to a computer-readable storage medium for causing a computer to control the supply of power by such a power supply control method.
2. Description of the Related Art
Conventionally, a power supply control apparatus controls the supply of power via an UPS to a computer system or the like when a power failure or a voltage drop occurs.
FIG. 1
is a system block diagram showing an example of a conventional power supply control apparatus. A computer system shown in
FIG. 1
includes an UPS
10
, a processing unit
11
, and a peripheral unit
12
. The processing unit
11
forms the power supply control apparatus.
The UPS
10
is connected between the processing unit
11
and an A.C. power source
14
. The UPS
10
detects a power failure when no power is received from the A.C. power source
14
. When the power failure is detected, the UPS
10
supplies power from a battery unit thereof to the processing unit
11
and the peripheral unit
12
.
The processing unit
11
is connected to the UPS
10
and the peripheral unit
12
. The processing unit
11
and the UPS
10
are connected by an UPS interface
13
. The processing unit
11
and the peripheral unit
12
are connected via a remote cabinet interface (RCI)
28
. Information related to the supply of power to the peripheral unit
12
is notified to the processing unit
11
via the RCI
28
.
The peripheral unit
12
is connected to the UPS
10
and the computer system
12
, and the power is supplied to the peripheral unit
12
via the UPS
10
.
For example, when a power failure occurs at a position indicated by “x” in
FIG. 1
, the UPS
10
detects that no power is supplied from the A.C. power source
14
. When no power is supplied from the A.C. power source
14
, the UPS
10
notifies information indicating the generation of a power failure to the processing unit
11
via the UPS interface
13
. The processing unit
11
which is notified of the information continues to operate using the power supplied from the battery unit of the UPS
10
. At the same time, the processing unit
11
receives power supply information from the peripheral unit
12
via the RCI
28
.
The processing unit
11
which continues to operate using the power supplied from the battery unit of the UPS
10
monitors the UPS
10
until the power supply from the A.C. power source
14
is restored, within a monitoring time which is set depending on a power supply compensation time of the battery unit of the UPS
10
. After the monitoring time elapses, the processing unit
11
carries out a process to normally stop the computer system, and also notifies to the peripheral unit
12
information indicating a disconnection of the power supply. When the peripheral unit
12
is notified of the information indicating the disconnection of the power supply from the processing unit
11
, the power supply thereto is disconnected. The power supply to the processing unit
11
is disconnected when the processing unit
11
ends the process of normally stopping the system.
Accordingly, a backup power supply is made by the UPS
10
with respect to the processing unit
11
and the peripheral unit
12
when the power failure occurs, so that the system can be stopped normally.
Next, a description will be given of another example of the conventional power supply control apparatus which uses two power supply systems, by referring to FIG.
2
.
FIG. 2
is a system block diagram showing this other example of the conventional power supply control apparatus. In
FIG. 2
, those parts which are the same as those corresponding parts in
FIG. 1
are designated by the same reference numerals, and a description thereof will be omitted. A computer system shown in
FIG. 2
includes a processing unit
15
, two UPSs
10
a
and
10
b
, and peripheral units
16
and
17
.
The processing unit
15
is connected to the UPS
10
a
and the UPS
10
b
via the respective UPS interfaces
13
. The processing unit
15
is also connected to the peripheral unit
16
and the peripheral unit
17
via the respective RCIs
28
.
The UPS
10
a
is connected to an A.C. power source
18
, and supplies power to the processing unit
15
, the peripheral unit
16
and the peripheral unit
17
. On the other hand, the UPS
10
b
is connected to a A.C. power source
19
, and supplies power to the processing unit
15
and the peripheral unit
17
.
The peripheral unit
16
receives the power from a single power supply system of the UPS
10
a
. The peripheral unit
17
receives the power from two power supply systems of the UPS
10
a
and the UPS
10
b.
Accordingly, two UPSs
10
a
and
10
b
are provided in the computer system shown in
FIG. 2
, so as to cope with a unit which has a power receiving configuration to receive the power from a single power supply system and a unit which has a power receiving configuration to receive the power from two power supply systems. For example, when a power failure occurs at a position indicated by “x” in FIG.
2
and no power is supplied to the UPS
10
a
from the A.C. power source
18
, the process to disconnect the power supply in the computer system is not carried out if the other UPS
10
b
is normal, and the power supply is continued in this case. In this state, the UPS
10
a
supplies the power from the battery unit thereof.
Next, a description will be given of the internal structure of the UPS, by referring to FIG.
3
.
FIG. 3
is a system block diagram showing an example of the internal structure of the UPS
10
,
10
a
or
10
b.
In
FIG. 3
, when an A.C. voltage from an A.C. power supply is input to the UPS, the A.C. voltage is converted into a D.C. voltage by an A.C./D.C. converter
20
. The D.C. voltage is supplied via a charger
21
to a D.C./A.C. converter
22
or a battery unit
24
. When the D.C. voltage is supplied to the D.C./A.C. converter
22
, the D.C. voltage is converted into an A.C. voltage. On the other hand, when the D.C. voltage is supplied to the battery unit
24
, the battery unit
24
is charged thereby.
A control circuit
25
checks the voltage between the charger
21
and the battery unit
24
, to determine whether or not the A.C. voltage input is normal and whether or not the power is supplied normally from the battery unit
24
. When the control circuit
25
detects a power failure based on the D.C. voltage, the control circuit
25
notifies the processing unit
15
, for example, via the UPS interface
13
. In addition, the control circuit
25
supplies a power supply state indication
26
to a display panel (not shown) of the UPS, so as to display a message, turn on a indicator lamp or the like.
The A.C. voltage from the D.C./A.C. converter
22
is supplied to an external unit such as the peripheral unit
16
or
17
, via an A.C. switch
23
. Furthermore, when an abnormality is generated in the D.C./A.C. converter
22
, the A.C. switch
23
supplies to the peripheral unit the A.C. voltage which is supplied to the A.C. switch
23
via a bypass circuit
27
.
Therefore, the UPS
10
,
10
a
or
10
b
charges the battery unit
24
so that the power can be supplied to the external unit from the battery unit
24
in case of a power failure or the like.
When the power failure occurs at a position indicated by “x” in the power supply control apparatus having two power supply systems as shown in
FIG. 2
, the power is supplied from the battery unit of the UPS
10
a
since no power is supplied from the A.C. power source
18
. On the other hand, the UPS
10
b
supplies the power from the A.C. power source
19
. In this stat

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