Method and apparatus for controlling signal timing of cascaded s

Details Method and apparatus for controlling signal timing of cascaded s Method and apparatus for controlling signal timing of cascaded s

1992-03-24

1995-08-08

Kriess, Kevin A.

Boots, shoes, and leggings

364736, 36472416, 3642817, 3642303, 3642383, 364DIG1, 327270, 348409, 348415, G06F 738, G06F 1200

Patent

active

054407214

ABSTRACT:
Each of the signal processing units of a digital signal processing system is provided with a programmable timing delay unit having identical programming interface to control the signal timing of its signal processing circuitry. Additionally, a central timing unit is provided to the digital signal processing system to provide signal timing control inputs to the programmable timing delay units. Furthermore, a routing switcher is provided to the digital signal processing system to control configuration of the signal path, i.e. the order in which the signal is processed by all or a subset of the signal processing units of the digital signal processing system. As a result, the individual signal processing units are relieved the burden of providing circuitry for timing control, delay equalization and timing derivation. Furthermore, the timing offsets for the individual signal processing units may be easily recomputed for any signal path, thereby improving the reconfiguration flexibility of the digital signal processing system.

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patent: 5081604 (1992-01-01), Tanaka
patent: 5155852 (1992-10-01), Murakami et al.

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