Method and apparatus for controlling power states in a...

Details Method and apparatus for controlling power states in a... Method and apparatus for controlling power states in a...

2006-02-14

2006-02-14

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S321000, C713S323000

Reexamination Certificate

active

07000133

ABSTRACT:
A method of controlling power states in a memory device includes determining if a power-down command is received. A first lower power state is entered if the power-down command is received and the memory device is in a first state. A second lower power state is entered if the power-down command is received and if the memory device is in a second state. The second lower power state is lower than the first lower power state. The memory device remains in a normal operation power state if the power-down command is not received.

REFERENCES:
patent: 5715465 (1998-02-01), Savage
patent: 5928365 (1999-07-01), Yoshida
patent: 6112306 (2000-08-01), Volk
patent: 6230274 (2001-05-01), Stevens
patent: 6349050 (2002-02-01), Woo et al.
patent: 6754783 (2004-06-01), Tsern et al.

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