Optics: measuring and testing – Inspection of flaws or impurities – Surface condition
Reexamination Certificate
1999-10-05
2001-07-10
Bowers, Charles (Department: 2813)
Optics: measuring and testing
Inspection of flaws or impurities
Surface condition
C430S030000
Reexamination Certificate
active
06259521
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to photolithography techniques for patterning semiconductor devices, and, more particularly, to a method and apparatus for controlling photolithography parameters based on photoresist images.
2. Description of the Related Art
Conventionally, semiconductor devices are patterned using photolithographic processes. A base material, such as a substrate material, a metal, an insulator, etc., is coated with a light sensitive material, referred to as a photoresist material. The photoresist is generally a composition that is sensitive to active rays of light, such as ultraviolet rays, X-rays or electron rays. The photoresist is deposited on the base material to selectively protect non-process portions of the substrate. Light is then selectively directed onto the photoresist film through a photomask, or reticle, to form photoresist patterns on the base material. The photoresist is then developed to remove either the exposed photoresist or the unexposed photoresist.
There are generally two types of photoresist, namely positive type and negative type. The positive photoresist is of such a type that the exposed portion dissolves in the developer, while the unexposed portion does not dissolve therein, and the negative photoresist is of the opposite type. Certain photoresist materials do not complete the transition from being soluble to being insoluble in the developer based solely on the exposure to light. These photoresist materials, referred to as chemically-amplified photoresists, are subjected to a post exposure bake process to complete the chemical reaction to transition from soluble to insoluble (i.e., for a positive resist).
A known technique for evaluating the acceptability of the photolithography process involves measuring critical dimensions or other parameters after the photoresist has been developed. One method to evaluate the developed wafer is to use scatterometry to generate an intensity measurement indicative of the pattern on the wafer. The pattern in the developed photoresist appears as a series of trenches. Light is reflected differently in the trenched vs. the non-trenched areas, resulting in a characteristic scattering pattern. The scatterometry measurements may be used to change the photoresist operating parameters, such as exposure time, post exposure bake time, develop time, etc. to affect the pattern formed on subsequent lots of wafers. A limitation of a post develop measurement technique is that significant time elapses between the measurement and the corrective action, potentially resulting in numerous unusable wafers.
The process of using a chemically-amplified photoresist is described in greater detail in reference to
FIGS. 1A through 1D
.
FIG. 1A
shows a wafer
10
including a base material
12
with a photoresist layer
14
deposited thereon. In
FIG. 1B
, the photoresist layer
14
is exposed to a light source through a reticle (not shown) to define exposed regions
16
. Exposure to the light causes hydrogen free radicals to form in the exposed regions
16
. In
FIG. 1C
, the wafer
10
is subjected to a post exposure bake to complete the solubility transition chemical reaction and form baked regions
18
. During the post exposure bake, the free radicals diffuse laterally and react with the photoresist
14
around the exposed regions
16
. Typically, for a deep UV photoresist layer
14
, the post exposure bake time is about 60-90 seconds. As shown in
FIG. 1D
, a developer may then be applied to remove the remaining photoresist
14
(i.e., for a negative resist—not shown) or to remove the baked portions
18
(i.e., for a positive resist—shown in FIG.
1
D).
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for controlling uniformity in a wafer. A wafer is provided. A photoresist layer is formed on the wafer, and the photoresist layer is patterned. A portion of the patterned photoresist layer is illuminated in at least first and second positions. Light reflected at the two positions is measured to generate first and second measurements. A recipe of a stepper is adjusted in response to the first measurement differing from the second measurement.
Another aspect of the present invention is seen in a wafer processing system including a stepper, a scatterometer, and a process controller. The stepper is adapted to expose a layer of photoresist in accordance with a recipe to generate an exposed layer of photoresist. The scatterometer is adapted to take first and second measurements in at least first and second positions on the exposed layer of photoresist. The process controller is adapted to compare the first and second measurements and adjust the recipe based on the first and second measurements.
REFERENCES:
patent: 5393624 (1995-02-01), Ushijima
patent: 5867276 (1999-02-01), McNeil et al.
Bishop et al., “Use of Scatterometry for resist process control,” SPIE Integrated Circuit Metrology, Inspection and Process Control, 1673:441-452, 1992.
Hickman et al., “Use of diffracted light from latent images to improve lithography control,” SPIE Integrated Circuit Metrology, Inspection and Process Control, 1464:245-257, 1991.
McNeil et al., “Scatterometry applied to microelectronics processing—Part 1,” Solid State Technology, 37(3):29-56, 1993.
Miller and Mellicamp, “Development of an end-point detection procedure for the post-exposure bake process,” Integrated circuit metrology, inspection, and process control IX: 20-22, Feb., 1995, Santa Clara, California, SPIE Integrated Circuit Metrology, Inspection and Process Control, 2439:78-88, 1995.
Milner et al., “Latent image exposure monitor using scatterometry,” SPIE Integrated Circuit Metrology, Inspection and Process Control, 1673:274-283, 1992.
Prins et al., “Scatterometric sensor for PEB process control,” Metrology, inspection, and process control for microlithogtaphy, X:11-13, Mar., 1996, Santa Clara, California, SPIE Integrated Circuit Metrology, Inspection and Process Control,2725:710-719, 1996.
Raymond et al., “Multiparameter process metrology using scatterometry,” In: Optical characterization techniques for high-performance microelectronic device manufacturing II, SPIE—The International Society for Optical Engineering, 2638:84-93, Austin, Texas, Oct. 25-26, 1995.
Raymond et al., “Scatterometric sensor for lithography,” Manufacturing process control for microelectronic devices and circuits, SPIE—The International Society for Optical Engineering, 2336:37-49, Austin, Texas, Oct. 20-21, 1994.
Sturtevant et al., “Post-exposure bake as a process-control parameter for chemically-amplified photoresist,” Metrology, inspection, and process control for microlithogtaphy, VII:2-4, Mar., 1993, Santa Jose, California, SPIE Integrated Circuit Metrology, Inspection and Process Control, vol. 1926, 1993.
Sturtevant et al., “Use of scatterometric latent image detector in closed loop feedback control of linewidth,” SPIE Integrated Circuit Metrology, Inspection and Process Control, 2196:352-359, 1994.
Goodwin Greg
Miller Michael
Advanced Micro Devices , Inc.
Bowers Charles
Pert Evan
Williams Morgan & Amerson P.C.
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