Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-03-21
2003-11-04
Le, Don (Department: 2811)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S087000
Reexamination Certificate
active
06642742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to controlling the output impedance of a driver circuit.
2. Description of the Related Art
Controlling the output impedance of drivers in an integrated circuit is of critical importance. Integrated circuits must often times drive signals onto signal lines of varying lengths and impedances. Matching the driver output impedance to that of the signal line may be necessary in order to prevent various effects from occurring. For example, signal reflections due to mismatched impedances may cause a receiving circuit to read an incorrect logic value. These problems can become more acute in high-speed interfaces, thus making impedance matching all the more critical in the design of newer generations of greater operating speeds.
It is most often desirable to control the output impedance of an integrated circuit driver within the chip itself. Controlling the impedance with resistors external to the chip may be impractical if not impossible. Thus, typical driver circuits often include some sort of impedance matching mechanism within the chip. Often times, transistors are used as the impedance matching mechanism. Typically, a plurality of transistors are used (as opposed to a single transistor) due to process, voltage, and temperature variations. The transistors may be connected in parallel between pairs of their respective terminals (e.g. the source and drain terminals of field effect transistors). The resistance, or impedance, on an output node may be controlled by activating one or more of the transistors. The transistors may be of substantially equal impedances, and therefore the impedance step sizes may vary as more transistors are activated.
SUMMARY OF THE INVENTION
A method and apparatus for controlling output impedance of an input/output (I/O) circuit is disclosed. In one embodiment, an I/O circuit may include a first plurality of resistive elements connected in parallel between a first reference node and an output node and a second plurality of resistive elements connected in parallel between the output node and a second reference node. Each of the resistive elements may include a control terminal. The control terminal may be used to activate or deactivate the resistive element. The control terminal for each resistive element may be controlled by a control circuit, which may be configured to activate one or more of the resistive elements. Each of the resistive elements of the first plurality may be of substantially different resistances, as may be true with the second plurality of resistive elements. Due to the substantially different resistances of each of the resistive elements of the first and second pluralities, the resistive step sizes for the I/O circuit may remain substantially equal as additional resistive elements are activated.
In one embodiment, the resistive elements may be field effect transistors. A gate terminal may be used as the control terminal, and may be coupled to the control circuit. For the first plurality of transistors, the drain and source terminals of each may be coupled between a voltage node and an output node. For the second plurality of transistors, the drain and source terminals may be coupled between the output node and a reference node (e.g. a ground node). When the I/O circuit is performing a transmission at a logic high voltage, the control circuit may activate one or more of the first plurality of transistors in order to achieve the desired output impedance. When performing a transmission at a logic low level, the control circuit may activate one or more of the second plurality of transistors. The activation of one or more transistors of either the first plurality or second plurality may terminate the output node of the I/O circuit such that the output impedance substantially matches the impedance of a signal line to which it is connected. Matching the impedances of the output node and the signal line may allow for a maximum amount of signal strength to be transmitted while minimizing the amount of signal reflection that may otherwise occur on the-signal line.
In one embodiment, the transistors of each plurality may be of substantially different physical sizes, and consequently, may provide different amounts of resistance when activated. This may result in resistance step sizes being substantially equal as additional transistors are activated. For example, a first transistor may provide a nominal resistance (impedance) of 92 ohms. A second transistor may provide a nominal impedance of 1722 ohms. However, the parallel combination of these two transistors may produce a total resistance of 87 ohms. A third transistor may have a nominal resistance of 1547 ohms; the parallel combination of the first, second and third transistors may yield a resistance of 83 ohms. Thus, the step size resulting from the activating of successive transistors is, in this embodiment, between 4 and 5 ohms, and may be achieved by using transistors of different physical sizes.
REFERENCES:
patent: 5134311 (1992-07-01), Biber et al.
patent: 5298800 (1994-03-01), Dunlop et al.
patent: 5313118 (1994-05-01), Lundberg
patent: 5457407 (1995-10-01), Shu et al.
patent: 5739707 (1998-04-01), Barraclough
patent: 5760601 (1998-06-01), Frankeny
patent: 5898321 (1999-04-01), Ilkbahar et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6127862 (2000-10-01), Kawasumi
patent: 6157215 (2000-12-01), Gabara et al.
patent: 6194924 (2001-02-01), Welch et al.
patent: 6225819 (2001-05-01), Rees et al.
patent: 2002/0093363 (2002-07-01), Wey et
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Le Don
Meyertons Hood Kivlin Kowert & Goetzel P.C.
LandOfFree
Method and apparatus for controlling output impedance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for controlling output impedance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for controlling output impedance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3142716