Method and apparatus for controlling operation of a cache memory

Details Method and apparatus for controlling operation of a cache memory Method and apparatus for controlling operation of a cache memory

1991-10-28

1994-12-06

Black, Thomas G.

395650, G06F 1208

Patent

active

053718720

ABSTRACT:
The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.

REFERENCES:
patent: 3827029 (1974-07-01), Schlofterer et al.
patent: 4001783 (1977-01-01), Monahan et al.
patent: 4028664 (1977-06-01), Monahan et al.
patent: 4075686 (1978-02-01), Calle et al.
patent: 4190885 (1980-02-01), Joyce et al.
patent: 4357656 (1982-11-01), Saltz et al.
patent: 4386402 (1983-05-01), Toy
patent: 4426682 (1984-01-01), Riffe et al.
patent: 4504902 (1985-03-01), Gallaher et al.
patent: 4635186 (1987-01-01), Oman et al.
patent: 4730248 (1988-03-01), Watanabe et al.
patent: 4811209 (1989-03-01), Rubinstein
patent: 4814981 (1989-03-01), Rubinfeld
patent: 4823256 (1989-04-01), Bishop et al.
patent: 4831581 (1989-05-01), Rubinfeld
patent: 4833601 (1989-05-01), Barlow et al.
patent: 4864492 (1989-09-01), Blakely-Fogal et al.
patent: 4881163 (1989-11-01), Thomas et al.
patent: 4887204 (1989-12-01), Johnson et al.
patent: 4896291 (1990-01-01), Gest et al.
patent: 4930106 (1990-05-01), Danilenko et al.
patent: 5014240 (1991-05-01), Suzuki
patent: 5060144 (1991-10-01), Sipple et al.
patent: 5091845 (1992-02-01), Rubinfeld
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5119484 (1992-06-01), Fox
patent: 5129090 (1992-07-01), Bland et al.
patent: 5146603 (1992-09-01), Frost et al.
patent: 5163143 (1992-11-01), Culley et al.
Harboe et al., "Multi-Tasking Using Coequal Multiple Microprocessors Having Memory-Lock Facilities" IBM Tech. Disc. Bull. vol. 24, No. 6 (Nov. 1981) pp. 2782-2785.

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