Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate
1999-09-17
2004-04-27
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
C711S100000, C711S154000
Reexamination Certificate
active
06728824
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to multimedia system performance. More particularly, the present invention relates to methods and apparatus for controlling an incoming multi-channel bitstream.
There has been a rapid evolution from analog video technology to digital video technology because of the advantages that digital video has to offer. Digital video can be stored and distributed more cheaply than analog video because digital video can be stored on randomly accessible media such as magnetic disc drives (hard disks) and optical disc media known as compact (CDs). Once stored on a randomly accessible media, digital video may become interactive, allowing it to be used in games, catalogs, training, education, and other applications.
One of the newest products to be based on digital video technology is the digital video disc, sometimes called “digital versatile disc” or simply “DVD.” These discs are the size of an audio CD, yet hold up to 17 billion bytes of data, 26 times the data on an audio CD. DVD storage capacity (17 Gbytes) is much higher than CD-ROM (600 Mbytes) and a DVD can deliver the data at a higher rate than CD-ROM. Therefore, DVD technology represents a tremendous improvement in video and audio quality over traditional systems such as televisions, VCRs and CD-ROM.
FIG. 1
is a block diagram showing a prior art multimedia system
10
. The multimedia system
10
includes a DVD channel decoder
12
, an external user/host computer
14
, an external memory
16
, a video encoder
18
, a monitor
19
, an audio playback
20
, speakers
21
, and an audio/video decoder chip
22
. The audio/video decoder chip
22
includes an input front end
23
, an audio/video decoding datapath
28
, a display controller
30
, an external memory interface
32
, an external host interface
34
, a synchronization module
36
, and an audio interface
38
. The input front end
23
includes an input parser
24
and a bitstream buffer controller
26
.
In operation, the input parser
24
receives a bitstream from the DVD channel decoder
12
. The input parser
24
processes the bitstream and passes it to the bitstream buffer controller
26
, which in turn processes the bitstream and passes it to the external memory
16
using the external memory interface
32
. The bitstream then travels from the external memory
16
to the audio/video datapath
28
, again using the external memory interface
32
. Next, the display controller
30
receives decoded picture data from the audio/video datapath
28
and passes the decoded picture data to the video encoder
18
, which then displays a video image using the monitor
19
. Also, the audio interface
38
receives decoded audio data from the audio/video datapath
28
and passes the decoded audio data to the audio playback
20
, which plays the audio using the speakers
21
.
In addition, the audio, video, and other bitstream data are synchronized throughout the system by the synchronization module
36
. Furthermore, additional parameters provided by the external user/host computer
14
are passed to the rest of the system
10
by the external host interface
34
.
FIG. 2
is a block diagram showing a prior art input front end
23
. The input front end
23
includes an input parser
24
and a bitstream buffer controller
26
. The bitstream buffer controller
26
includes a buffer memory
40
and a memory controller
42
.
In use, the input parser receives a bitstream
44
, parses the bitstream
44
into a data type
50
and associated data
52
, and provides the data type
50
and associated data
52
to the bitstream buffer controller
26
. The bitstream
44
typically includes video data, audio data, sub-picture data, and navigation data. The input parser recognizes the type of data being received and provides the data type information
50
to the bitstream buffer controller
26
, along with the associated data
52
. Since other system components are generally unable to distinguish the type of data being received, the data type
50
is stored with each data word
52
. Then, during read operations, the data type is provided to system components along with the associated data
52
from the buffer memory.
When the memory controller
42
receives a signal to write data to the buffer memory
40
, the memory controller provides a memory address for writing the data type
50
and the associated data
52
to the buffer memory
40
. Later, when the data
52
needs to be read by other system components, the memory controller
42
provides the address for the requested data. The data type
50
and associated data
52
are then provided to the rest of the system. It should be noted that both the data type
50
and the associated data
52
are written in the buffer memory in a conventional bitstream buffer controller.
One problem with the conventional bitstream buffer controller is that both the data type and the associated data are stored in the buffer memory, resulting in less buffer memory being available for actual data. Generally, the additional bits required to store the data type increase the amount of buffer memory needed to support the system. The additional buffer memory then results in increased manufacturing cost.
Additionally, the conventional bitstream buffer controller is generally not flexible enough to support high speed hardware. Typically, the bitstream buffer controller receives and sends data at 27 MHz. However, new system components often require data to be sent at 81 MHz. Since the conventional bitstream buffer controller often cannot provide data at 81 MHz, many new system components may not be supported by a conventional bitstream buffer controller.
In view of the forgoing, what are need are improved methods and apparatuses for controlling incoming multi-channel bitstreams. The methods should be able to operate with reduced memory, and should be flexible enough to support 81 MHz data access.
SUMMARY OF INVENTION
The present invention addresses these needs by providing a memory controller for an incoming multi-channel bitstream. In one embodiment, the memory controller includes a computer memory having an address range, a plurality of memory controllers, and a selector coupling the memory controllers to the computer memory. Each memory controller is capable of providing an address within the address range of the computer memory. In use, the selector selects a memory controller based on a received data type in an incoming bitstream. The selector then provides an address received from the selected memory controller to the computer memory.
In another embodiment, a method for controlling a memory storing a portion of an incoming bitstream is disclosed. The method comprises receiving an incoming bitstream having a data type and associated data. Next, a memory controller is assigned to the data type based on the availability of appropriate memory controllers. Finally, the associated data is then written to computer memory using the memory controller assigned to the data type.
In yet another embodiment, a request for data is received. Next, the selector determines an appropriate memory controller to read the requested data from computer memory. This determination typically includes, among other things, checking to see if the requested data is still available in the computer memory. Finally, the requested data is read from the computer memory utilizing the appropriate memory controller.
Advantageously, the use of various memory controllers allows the present invention to store data from an incoming bitstream without storing an associated data type for each data word. Unlike conventional bitstream buffers that store the data type along with each data word, the present invention avoids this by keeping track of which memory controller is currently assigned to each memory type.
In addition, the present invention allows data access at 81 MHz. By keeping track of the amount of data stored in each memory address range, the present invention knows ahead of time how much data of a particular data type needs to be read from memory. This allow
NJR Corporation
Thai Tuan V.
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