Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-07-09
2002-11-12
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S147000, C710S200000, C709S213000, C713S152000
Reexamination Certificate
active
06480945
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a control method for a common memory device on a network, and a memory system made up of the common memory device and a plurality of access apparatuses for writing data in the common memory device.
A known memory system of this type comprises a plurality of computers connected to a network and used as access apparatuses, and a memory device such as a hard disk connected to the network and accessed by each computer via the network to rewrite data. Another known system comprises a plurality of CPUs (Central Processing Units) connected to a CPU bus, and a RAM (Random Access Memory) accessed by each CPU via the bus to rewrite data. Still another known system comprises a plurality of memory-accessible cards connected to a back plane bus, and a memory device commonly accessed by the cards to rewrite data.
Hardware or software exclusively controls these memory systems to avoid contention of access from each memory access apparatus to the common memory device.
In exclusive control by hardware, an exclusive control flag is arranged at a connection portion between the common memory device and each memory access apparatus. A given memory access apparatus, which accesses the common memory device, sets the flag for itself, writes data in the common memory device, and resets the flag at the end of write access. While the given memory access apparatus accesses the common memory device, other memory access apparatuses are inhibited from accessing the common, memory device.
In exclusive control by software, a flag area is allocated in part of a memory in the common memory device. A given memory access apparatus, which accesses the common memory device, sets the flag for itself, writes data in the common memory device, and resets the flag at the end of write access.
In exclusive control by hardware, it is difficult to accurately set the flags in response to flag setting requests from a plurality of memory access apparatuses operating asynchronously at high speed. When the respective memory access apparatuses output flag setting requests, no flags corresponding to the apparatuses may be set, or some flags for the corresponding apparatuses may be set. The exclusive control by hardware requires a logic circuit for confirming whether each flag is correctly set or reset, resulting in a complicated hardware arrangement. When a memory access apparatus, which has set the flag, does not reset the flag, the common memory device cannot be used. A means for monitoring this state and restoring the memory accessible state must be arranged to result in a complicated hardware arrangement. The common memory device can process a request from only one memory access apparatus at a time. Other memory access apparatuses, which have accessed the common memory device simultaneously with the currently accessing apparatus, must wait for data rewrite. The processing efficiency undesirably decreases.
The exclusive control by software requires a process for preventing contention between a given memory access apparatus and other memory access apparatuses when the given memory access apparatus sets its own flag in the flag area in the common memory device. This complicates a software process. When the memory access apparatus, which has set the flag, does not reset the flag, the common memory device cannot be used. A processing means for appropriately monitoring such a flag state and restoring the memory accessible state is required. This also complicates the software process.
SUMMARY OF THE INVENTION
It is an object of the present invention to allow rewriting data in a common memory device for a plurality of memory access apparatuses without complicating a hardware arrangement and software process and prevent a decrease in processing efficiency of memory access apparatuses in rewriting data.
In order to achieve the above object of the present invention, there is provided a memory device control method comprising the first step of causing a first access apparatus to transmit first data previously written and second data to be newly written as a pair of data to a memory device which stores data corresponding to a plurality of access apparatuses including the first access apparatus, the second step of determining whether data stored in correspondence with the first access apparatus coincides with the first data when the memory device receives the pair of data, and the third step of allowing writing the second data in the memory device when the data stored in the memory device coincides with the first data, and rejecting to write the second data when the data stored in the memory device does not coincide with the first data.
REFERENCES:
patent: 5375243 (1994-12-01), Parzych et al.
patent: 5719941 (1998-02-01), Swift et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Tran Denise
Yamatake Corporation
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