Method and apparatus for controlling line eviction in a cache

Details Method and apparatus for controlling line eviction in a cache Method and apparatus for controlling line eviction in a cache

2005-11-22

2005-11-22

Elmore, Stephen C. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S125000, C711S144000, C711S145000, C711S156000

Reexamination Certificate

active

06968429

ABSTRACT:
One embodiment of the present invention provides a system for controlling cache line eviction. The system operates by first receiving a sequence of instructions at a processor during execution of a program, wherein the sequence of instructions causes a cache line to be loaded into the cache. Next, the system examines the sequence of instructions to determine if an associated cache line includes only scratch data that will not be reused. If so, upon loading the cache line into the cache, the system marks the cache line as containing only scratch data, which allows the cache line to be evicted next from the cache.

REFERENCES:
patent: 5732242 (1998-03-01), Mowry
patent: 6886085 (2005-04-01), Shuf et al.
patent: 6910107 (2005-06-01), Boucher
Kessler et al., “The Alpha 21264 Microprocessor Architecture,” pp 1-6, Nov. 1999.
Ding et al., “Improving Cache Performance in Dynamic Applications through Data and Computation Reorganization at Run Time,” pp 229-241, ACM, May 1999.
Wang et al., “Using the Compiler to Improve Cache Replacement Decisions,” pp 199-208, IEEE, Sep. 2002.

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