Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt prioritizing
Reexamination Certificate
1999-12-23
2003-09-09
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt prioritizing
C710S262000, C710S266000
Reexamination Certificate
active
06618780
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention pertains to a method and apparatus for controlling interrupt priority resolution in a computer system or the like. More particularly, the present invention pertains to a method and system to dynamically control the determination of interrupt priority.
In a computer system or the like, a processor or other similar computing device may receive one or more interrupt requests generated internally or from peripheral devices coupled to the processor. When an interrupt is received by a processor, it typically suspends the processing that is currently being performed, stores the values currently loaded in its registers and begins execution of code to respond to the interrupt request.
As computer systems become more complex, more and more devices are given the opportunity to generate interrupt requests to the processor. Sometimes, interrupt requests may be received simultaneously by the processor. In other situations an interrupt request may be received while another interrupt request is being handled. This poses a problem for the designer in that processing of some interrupts may be so critical to the computer system that the servicing of inferior interrupt requests may negatively impact system operation.
One option for the computer system designer is to provide some sort of system that allows for one interrupt request to have priority over another. In such a device when two or more interrupts are received simultaneously, either the processor executing software code or, a logic device external to the processor (e.g., by looking to input pins that have a preassigned priority order), determines which of the interrupts has a higher priority and services the highest priority interrupt first. There are several drawbacks to such a system. First, the setting of the priority is static in that once the priority is set between two or more interrupts, that priority is maintained throughout the operation of the computer system. Second, when a computer system is handling a low priority interrupt, it will complete servicing of that interrupt before servicing higher-priority interrupts. If higher-priority interrupts (or those interrupts that later become a higher priority) are not handled quickly, there could be a negative impact on computer system performance. Finally, a software-based approach to resolving interrupt request priorities may take many instruction cycles and result in long latencies in servicing interrupts.
In view of the above, there is a need for a system and method that provides a quicker interrupt priority resolution and faster interrupt servicing in a computer system.
SUMMARY OF THE INVENTION
A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt. If the newly asserted interrupt request has a priority that is less than the priority of the currently serviced interrupt, the lower-priority interrupt is prevented from being asserted to the processor (until at least the servicing of the higher-priority interrupt is complete, for example).
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Cirrus Logic Inc.
Ray Gopal C.
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