Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2000-05-23
2002-05-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S680000, C438S774000, C438S775000, C438S784000, C427S008000, C427S009000
Reexamination Certificate
active
06387823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device manufacturing, and, more particularly, to a method and apparatus for controlling a deposition process using residual gas analysis.
2. Description of the Related Art
In the manufacture of semiconductor devices, wafers, such as silicon wafers, are subjected to a number of processing steps. The processing steps include depositing or forming layers, patterning the layers, and removing portions of the layers to define features on the wafer. One such process used to form the layers is known as chemical vapor deposition (CVD), wherein reactive gases are introduced into a vessel, e.g., a CVD tool, containing the semiconductor wafers. The reactive gases facilitate a chemical reaction that causes a layer to form on the wafers. One exemplary deposition process is the formation of polysilicon in a furnace by reacting nitrogen (N
2
) and silane (SiH
4
) in a furnace.
There are many factors that affect the deposition rate of a deposition tool. These factors include, among other things, the flow rate of reactive gases through the chamber and the temperature of the chamber. Typically, to determine the deposition rate for a particular tool (e.g., when it is first placed in service or after a maintenance event), a series of qualification wafers are processed and the resultant thickness of the process layer is measured. The measurements are used to estimate the deposition rate of the tool. Deposition times for subsequently processed wafers are determined based on the anticipated deposition rate. Normal variations in temperature and reactant flow rate may cause a deviation in the deposition rate from the anticipated rate, causing the process to exceed a control limit. Statistical processing is typically conducted on a sample of wafers in each lot to determine if the deposition process yielded a process layer thickness within an acceptable range. In some cases, the post-process metrology data is not available prior to processing another lot of wafers in the tool. A deviation out of the acceptable range might not be detected in time, resulting in two lots out of specification. Thickness variations can result in reduced equipment utilization and availability. Also, the thickness variations must be accounted for in subsequent processing steps. Generally, a greater process variation results in a more costly and less efficient processing system. Post-process sampling provides some measure of process performance, but not at a level suitable for lot-by-lot process control in a high-volume production facility.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for controlling a deposition process. The method includes providing a wafer in a chamber of a deposition tool, the deposition tool being adapted to operate in accordance with a recipe; providing reactant gases to the chamber, the reactant gases reacting to form a layer on the wafer; allowing exhaust gases to exit the chamber; measuring characteristics of exhaust gases; and changing the recipe based on the characteristics of the exhaust gases.
Another aspect of the present invention is seen in a deposition tool including a chamber, a gas supply line, a gas exhaust line, a gas analyzer, and a controller. The chamber is adapted to receive a wafer. The gas supply line is coupled to the chamber for providing reactive gases. The gas exhaust line is coupled to the chamber for receiving exhaust gases. The gas analyzer is coupled to the gas exhaust line and adapted to determine characteristics of the exhaust gases. The controller is adapted to control the processing of the wafer in the chamber based on the characteristics of the exhaust gases.
REFERENCES:
patent: 5273423 (1993-12-01), Shiraiwa
patent: 5712702 (1998-01-01), McGahay et al.
patent: 5897710 (1999-04-01), Sato et al.
patent: 6264706 (2001-07-01), Hirano
Sonderman Thomas
Toprac Anthony J.
Advanced Micro Devices , Inc.
Bowers Charles
Kilday Lisa
Williams Morgan & Amerson P.C.
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