Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-01-02
2000-11-14
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711105, 711150, 711151, 711158, 711167, 711169, G06F 1300
Patent
active
06148380&
ABSTRACT:
An interface and method for a synchronous DRAM (syncDRAM) memory are provided that improve performance. The read operation in a syncDRAM is significantly sped up by eliminating the step of opening a new page of data in a SyncDRAM using a speculative read method. This provides the ability to open a page of information in the SyncDRAM with a command generator in response to a data request. Speculative read logic is also included to continue reading from the page with an invalid address until a second read request occurs. Thus, in the event that a subsequent read request occurs that requests data located on the same page as the prior request, the data can be indexed and read from a location on that page without having to first assert the SCS# and SCAS#. This frequently removes the step of opening a page from the read process and, over time, can significantly speed up the overall SyncDRAM reads in a computer system.
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Dodd James M.
Malinowski Richard
Cabeca John W.
Intel Corporation
Tzeng Fred F.
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