Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
1998-12-10
2001-06-05
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C711S167000, C711S105000, C709S232000, C365S233100
Reexamination Certificate
active
06243768
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to data communications in a computer system and, more particularly, to memory control design to support synchronous Dynamic Random Access Memory (DRAM) memory.
DESCRIPTION OF RELATED ART
In conventional central processing unit (CPU) design, speed in which data is transferred within the CPU has been increasing rapidly with the advent Reduced Instruction Set (RISC) architectures and even more so due to extensive use of pipelining. However, unlike CPU development, development of different types of memory has concentrated on increasing media density in order to reduce the cost per bit of memory and not speed. This disparity has created an imbalance in memory bandwidth required for small low-cost systems. External interleaving to improve memory bandwidth has been employed to address this problem, but has failed. External interleaving has become a less favorable option due to use of asynchronous interfaces, high timing margins, high data rate, and a lack of registers for control signals, addresses and Input/Outputs (I/Os). The cost external interleaving is also high due to additional glue logic and total memory density required for a given bandwidth. This imbalance created the need for synchronous DRAM-type memory units (syncDRAMs).
SyncDRAMs offer increased memory density with low cost and high bandwidth memory architecture. Furthermore, syncDRAMs are able to support various applications like mainstore, peripherals, graphics and video. SyncDRAMs are designed for a wide range of applications with programmable features such as latency, burst length and burst-type. They can support single or dual bank high frequency and low power operations.
A key feature provided by syncDRAMs is immediate access to multiple blocks of data called “bursts”. Burst length refers to the number of words that will be output or input in a read or write cycle respectively. After a read burst has completed, the output bus will become high impedance. The burst length is programmable as 1, 2, 4 or 8 words, or a full page. The ability of the CPU to access these bursts of information give the CPU access to wider bandwidth of memory.
In operation, the syncDRAM is enabled by a command from a memory control unit responding to a data transfer request from the CPU. The syncDRAM responds by enabling an internal clock (CKE#) to begin the command cycle when the clock enable pin is asserted. An address is then internally latched by the syncDRAM from which data will be read or written to. Each time a burst of data is requested, the syncDRAM must go through the initiation sequence in order to access the address from which data will be read or written. The time it takes to complete the initiation process will deficit the overall memory retrieval time needed to access the data.
SUMMARY OF THE INVENTION
According to the invention, there is provided method of performing a burst transfer of data between a memory resource and a device. A burst transfer of data between the memory resource and the device is initiated. If the burst transfer is allowable, a portion of the data is transferred between the memory resource and device and an access address is incremented to reference a subsequent location in the memory resource. If the burst transfer is not allowable, a sequence of back-to-back operations is performed with respect to the access address until the burst transfer becomes allowable.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Hong
Yoo Do Hyun
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