Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-06-10
2009-02-17
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07493583
ABSTRACT:
A method for controlling crosstalk, power and yield in nanometer-technology integrated circuits (“ICs”) is based on a performance driven space optimization technique that minimizes the coupling capacitance between the interconnecting wires. Given a routed IC design, virtual compression-springs are inserted between all the elements of the design creating a mesh of springs. The design is then perturbed, or shaken, by transforming the spring system into a minimum-energy problem, a solution for which reduces or eliminates crosstalk violations, minimizes power and increases yield as the springs reach minimum energy state. In a described method, the primitives of a given IC layout are defined in terms of object points. In a first step, a mesh of virtual compression springs connecting all the layout primitives is generated from the object points. The spring constant for each virtual spring embedded between interconnecting wires is chosen to follow a relationship between a slack function and the separation distance between the interconnecting wires. In a second step, the design is shaken by minimizing the energy of the virtual compression-spring-loaded-system, resulting in new object points and new positions for the springs and the interconnecting wires.
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He et al., “Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization”, Design Automation Conference 1998, pp. 373-378 (Feb. 1998).
Chiang Jack
Lin Aric
Olympic Patent Works PLLC
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