Method and apparatus for controlling compressed Z...

Computer graphics processing and selective visual display system – Computer graphics display memory system – For storing compressed data

Reexamination Certificate

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Details

C345S422000, C345S557000

Reexamination Certificate

active

06492991

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to video graphics processing and more particularly to a method and apparatus for managing compressed Z information in a video graphics system.
BACKGROUND OF THE INVENTION
Computers are used in many applications. As computing systems continue to evolve, the graphical display requirements of the systems become more demanding. This is especially true in the area of three-dimensional (3D) graphics processing. In order to process 3D graphics images, the position of graphics primitives with respect to the display must be understood in all three dimensions. This includes the dimension of depth, often referred to as the Z dimension. The Z dimension describes the positioning of a video graphics primitive with respect to other video graphics primitives within the display frame in terms of the depth, or distance from the viewer, of the video graphics primitives.
Computer displays and other high resolution display devices such as high definition televisions (HDTVs), projectors, printers, plotters, and the like, present an image to the viewer as an array of individual picture elements, or pixels. The individual pixels are given a specific color, which corresponds to the color of the image at the location of the particular pixel. The pixels are closely spaced, and the viewer's visual system performs a filtering of individual pixel colors to form a composite image. If the partitioning of the image into individual pixel elements is performed properly, and the pixels are close enough together, the viewer perceives the displayed array of pixels as a virtually continuous image.
In order to present a smooth and continuous image on the display, the processing entity processing the video graphics images must maintain a high rate of pixel processing. In order to achieve high rates of pixel processing, pixel data stored in memory must be retrieved, processed, and then stored back in the memory in an efficient manner. Pixel fragments that are received include a Z value and a color value corresponding to the fragment. These fragments also include X and Y coordinates that specify, with respect to the display frame, the particular pixel with which the fragment corresponds. The Z value of the fragment is compared with a stored Z value for the particular pixel, and if it is determined that the fragment is located in front of the pixel (the Z value of the fragment indicates less spatial depth), the Z value and color value corresponding to the fragment must be written in the memory that stores the data corresponding to that particular pixel. Typically, the memory storing the pixel information is referred to as the frame buffer.
In an example system that requires a 100 megapixel-per-second (100 M pixels/sec) pixel processing rate, the worst case scenario is the case where all of the fragments received are located in front of the pixels currently stored in the frame buffer. In such a scenario, 100 M read operations are required (on a per second basis) to fetch the Z data for the pixels from the frame buffer. If it is assumed that each Z value and each color value for a particular pixel requires two bytes, the rate of Z value reads from the frame buffer required to perform the comparison with the fragments will be 200 M bytes/sec. If all of the fragments are located in front of the pixel Z values currently stored, another 200 M bytes/sec will be required to store the Z values for the fragments in the frame buffer. Finally, if all of the fragments are in front of the current frame buffer information, 100 M color write operations per second will be required as the color values for the fragments must be stored in the frame buffer. Once again, if two bytes are required to store each color value, another 200 M bytes/sec of memory bandwidth is required. Thus, in the worst case scenario, the total memory bandwidth required for a 100 M pixels/sec rate is 600 M bytes/sec.
Assuming a more typical scenario in which 50 percent of the Z comparisons between the fragments and the currently stored pixel information result in the fragment data replacing the pixel data, the memory bandwidth requirements will be reduced to 400 M bytes/sec. This is due to the fact that the number of writing operations to the frame buffer will be cut in half. Even with this assumption in place, the amount of memory bandwidth required to perform 3D video graphics processing is substantial.
More memory bandwidth translates into increased cost. This can be due to the requirement for faster, more expensive memories or more memories that can operate in parallel. Parallel memory structures are undesirable as they add complexity to the system and can increase costs of manufacturing 3D graphics processing systems.
Therefore, a need exists for a method and apparatus for reducing the memory bandwidth requirements in a 3D video graphics system.


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patent: 5812138 (1998-09-01), Devic
patent: 5819017 (1998-10-01), Akeley et al.
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patent: 0603045 (1994-02-01), None
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European Search Seport for EP 00 30 6650.
Annex to the European Search Report for EP 00 30 6650.

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