Method and apparatus for controlling compensated buffers

Details Method and apparatus for controlling compensated buffers Method and apparatus for controlling compensated buffers

1997-03-24

1999-02-09

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 32, 327407, H03K 190175

Patent

active

058699830

ABSTRACT:
A method and an apparatus for controlling compensated buffer circuits. In one embodiment, a compensation buffer control circuit includes a compensation unit with a compensation signal memory location such as a compensation register. The compensation unit is configured to produce a local compensation control signal to control a compensated buffer circuit. The compensation signal memory location is configured to selectively receive and store and the local compensation control signal generated by the compensation unit. The contents of the compensation signal memory location may be read, which allows for the external reading of the local compensation signal generated by the compensation unit. In addition, an external write of an external compensation control signal may be performed to the compensation signal memory location such that the output of the compensation unit can be overridden. A compensated buffer circuit is coupled to selectively receive either the local compensation control signal or the external compensation control signal.

REFERENCES:
patent: 4975598 (1990-12-01), Borkar
patent: 5063308 (1991-11-01), Borkar
patent: 5306965 (1994-04-01), Asprey
patent: 5528166 (1996-06-01), Ikbahar
patent: 5736867 (1998-04-01), Keiser et al.
Donnelly KS et al.: A 660 MB/s Interface Megacell Portable Circuit in 0.3 .mu.m CMOS ASIC, IEEE J of Solid-State Circuits, vol. 31(12): Dec. 1996.
Gabara TJ et al.: Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers, IEEE J of Solid-State Circuits, vol. 32(3), Mar. 1997.

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