Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2008-04-22
2008-04-22
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C713S500000, C327S276000
Reexamination Certificate
active
08990420
ABSTRACT:
A method and apparatus is presented that can provide first and second windows for driving data onto a bus in dependence on bus clock frequency. In one example, the speed of the bus clock is determined by a component such as a processor. If the bus clock frequency is at a first, relatively high frequency, data is driven onto the bus in an earlier time window (e.g., near the rising edge of the bus clock signal). If the bus clock frequency is at a second, lower frequency, data is driven onto the bus in a second, later time window (e.g., near the center of the high level of the bus clock). Accordingly, the time window for receiving the data driven onto the bus need not be changed (e.g., near the rising edge of the next bus clock signal) allowing components to work effectively with both bus clock frequencies.
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Intel Corporation
Kenyon & Kenyon LLP
Rinehart Mark H.
Vu Trisha
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