Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-09-29
2001-09-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C365S239000
Reexamination Certificate
active
06288951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to voltage regulation, and more particularly, to a method and apparatus for continuously regulating an output voltage of the charge pump using a capacitor divider network.
2. Description of the Related Art
A non-volatile memory powered from a single low voltage power supply, V
CC
, typically employs a multi-phase voltage or charge pump to boost V
CC
to a high voltage VPP required for programming and erase operations. Further details for providing a multi-phase charge pump can be found in U.S. Pat. No. 5,263,000 by Van Buskirk entitled “Drain Power Supply ” and U.S. Pat. No. 5,511,026 by Cleveland entitled “Boosted And Regulated Gate Power Supply With Reference Tracking For Multi-Density And Low-Voltage Supply Memories ”, both incorporated by reference herein. The boosted voltage is regulated to provide stable programming and erase voltages.
FIG. 1
shows a voltage output of charge pump
110
of a non-volatile memory regulated by regulator
120
to generate a constant output voltage VPP.
FIG. 2
illustrates a circuit diagram of a typical prior art regulator
120
. The supply voltage V
CC
powering both charge pump
110
and regulator
120
is, for example, 3 V and the target output voltage of charge pump
110
, V
target
, is, for example, 9.5 V (it should be noted that all voltage values used herein are approximate values).
Accordingly, if capacitors C
1
and C
2
are metal capacitors, the voltage at node A is 0 V when the Enable (EN) input is at a logic LOW level and when the initial voltage of VPP is 3 V.
However, once an erase operation, for example, is initiated, the EN input transitions to a logic HIGH voltage level. This turns on P-MOS transistor T
1
, and the voltage at node A subsequently increases as charge pump
110
charges up the voltage at nodes B and D to VPP. The voltage at node C remains at 0 V until the voltage at node A exceeds a fixed reference voltage V
ref
. The target output voltage of charge pump
110
is at all times proportional to a ratio of the values of capacitors C
1
and C
2
. The following equation expresses this relationship:
V
target
=
V
ref
(
1
+
C
2
C
1
)
(
1
)
For certain values of capacitors C
1
and C
2
, the voltage at node A is 1.3 V if the target voltage is 9.5 V. However, if charge pump
110
charges VPP beyond the target voltage of 9.5 V, the voltage at node A rises above 1.3 V, and the output of comparator
210
(node C) will transition to a logic HIGH voltage level (since V
ref
is fixed at, for example, 1.3 V). This turns on transistor T
2
and transistor T
2
discharges VPP back down to the target voltage of 9.5 V.
While this feedback mechanism can be effective in regulating VPP to the target voltage, prior art regulator
120
is only effective for regulating relatively short output voltage pulses of charge pump
110
(e.g., up to 2-3 msec). This is because capacitors C
1
and C
2
, like all capacitors, leak charge over time. Consequently, if the output voltage pulses of charge pump
110
were, for example, 20 msec long, the steady state voltage at node A progressively dips below 1.3 V (under normal circumstances, the voltage at node A is 1.3 V when V
PP
is charged up to the target voltage of 9.5 V). In response, prior art regulator
120
compensates for this change in the voltage of node A by increasing the voltage at node B. In other words, regulator
120
tries to “pull ” the voltage at node A back up to 1.3 V by increasing the voltage at node B. The only way regulator
120
can increase the voltage at node B is to increase the voltage at node D, or VPP.
Thus, for long output voltage pulses of charge pump
110
, regulator
120
must increase VPP beyond the target voltage of 9.5 V to maintain the voltage of node A at 1.3 V. Regulator
120
may have to increase VPP to, for example, 11 V in order to maintain 1.3 V at node A. This result is undesirable because regulator
120
should regulate the voltage output of charge pump
110
at the target voltage (e.g., 9.5V) and not at any other voltage. Accordingly, there is a need for a regulator comprising a capacitor divider network that is capable of continuously regulating the output of charge pump
110
at some target voltage. A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.
SUMMARY OF THE INVENTION
The invention, roughly described, provides a method and apparatus for continuously regulating an output voltage of a charge pump of a non-volatile memory using a capacitor divider network. In particular, the invention provides a method for continuously regulating an output voltage of a non-volatile memory for long periods of time to a target output voltage wherein the non-volatile memory comprises a first regulator and a second regulator and the method comprises the steps of regulating the output voltage to the target voltage with the first regulator for a first period of time, inactivating the first regulator for a second period of time at the end of the first period of time, regulating said output voltage to the target voltage with the second regulator for a third period of time, at the end of the second period of time, while the first regulator is inactive, inactivating the second regulator for a fourth period of time at the end of the third period of time, and repeating the above steps at the end of the fourth period of time for as long as the output voltage needs to be regulated.
In one embodiment, the present invention is incorporated within a non-volatile memory comprising a charge pump and a regulator. The regulator comprises a first regulator sub-circuit, and a second regulator sub-circuit, each having a capacitor divider network. The first regulator sub-circuit regulates an output voltage of the charge pump at a target output voltage while the second regulator sub-circuit is disabled and said second regulator regulates the output voltage of the charge pump at the target output voltage while said first regulator sub-circuit is disabled.
Specifically, the first regulator sub-circuit regulates the output voltage of the charge pump at the target output voltage for a first period of time while the second regulator sub-circuit is disabled and, at the end of the first period of time, the first regulator sub-circuit is disabled for a second period of time and the second regulator sub-circuit is enabled so as to regulate the output voltage of the charge pump at the target output voltage for a third period of time while the second regulator sub-circuit is disabled. At the end of the third period of time, the second regulator sub-circuit is disabled for a fourth period of time and the first regulator sub-circuit is again enabled for the first period of time. By alternatively using the first and second regulator sub-circuits to regulate the output voltage of the charge pump at the target voltage, the present invention can regulate the output of the charge pump virtually indefinitely.
REFERENCES:
patent: 5754476 (1998-05-01), Caser et al.
patent: 5808506 (1998-09-01), Tran
patent: 5831845 (1998-11-01), Zhou et al.
patent: 5933047 (1999-08-01), Zhu et al.
patent: 6078212 (2000-06-01), Iakhani
patent: 6144606 (2000-11-01), Pan
Chen Pau-Ling
Le Binh Quang
Advanced Micro Devices
Fliesler Dubb Meyer & Lovejoy LLP
Le Thong
Nelms David
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