Method and apparatus for constructing and optimizing a skew...

Details Method and apparatus for constructing and optimizing a skew... Method and apparatus for constructing and optimizing a skew...

2008-07-29

2008-07-29

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07406672

ABSTRACT:
An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs, based on the clock tree, a plurality of groups each of which includes a part of elements of same skew; an analyzing unit that performs an analysis of a timing of an inter-group path between two of the groups; and an output unit that outputs a result of the analysis.

REFERENCES:
patent: 5980092 (1999-11-01), Merryman et al.
patent: 6698006 (2004-02-01), Srinivasan et al.
patent: 6799310 (2004-09-01), Miyamoto
patent: 7257782 (2007-08-01), Ho et al.
patent: 2004-185466 (2004-07-01), None

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