Method and apparatus for constructing a digital phase differenti

Details Method and apparatus for constructing a digital phase differenti Method and apparatus for constructing a digital phase differenti

1997-12-01

2000-06-06

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

326323, 326343, H03D 324

Patent

active

060728485

ABSTRACT:
A method and apparatus for constructing a digital phase differentiator incorporating a dynamic decrement counter (30). A limited signal is sampled at a fixed sampling rate. A fixed rate for an intermediate frequency is obtained. The fixed sampling rate is divided by a divisor to obtain a frequency of a clock. The frequency of the clock is divided by the intermediate frequency to obtain an desired average divider. A set of integer load values (34, 36 and 38) is selected that on average yields a non-integer value that is close to the desired average divider. A load of the dynamic decrement counter (30) changes cyclically using the set of integer load values (34, 36 and 38) to obtain a phase of the limited signal.

REFERENCES:
patent: 4286223 (1981-08-01), Shearer
patent: 4656431 (1987-04-01), Chapman
patent: 5469112 (1995-11-01), Lee
patent: 5844446 (1998-12-01), McAllister et al.

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