Method and apparatus for constraint graph based layout...

Details Method and apparatus for constraint graph based layout... Method and apparatus for constraint graph based layout...

2006-08-01

2006-08-01

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07086027

ABSTRACT:
A method of compacting a circuit layout includes determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit layout. The method further includes representing the critical path to include a plurality of vertices and a plurality of edges, each one of the vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge. The method further includes representing the flexible vertex to include a first jogging edge. The method further includes determining an optimal cutest of the graph of the critical path, the cutest including at least one of the group consisting of the first jogging edge and the first shear edge.

REFERENCES:
patent: 5984510 (1999-11-01), Guruswamy et al.
patent: 6434721 (2002-08-01), Chiluvuri et al.
Bamji, Cyrus et al; Incremental Autojogging Using Range Spaces; Proceedings Eleventh International Conference on VLSI Design; Jan. 4-7, 1998; pp. 265-268; XP-002162467; IEEE.
Dunlop, A.E.; SLIM-The Translation of Symbolic Layouts into Mask Data; Proceedings of the 17thDesign Automation Conference; Jun. 23-25, 1980; pp. 595-602; XP-000989688; IEEE.
Cho, Y. Eric; A Subjective Review of Compaction; Proceedings of the Design Automation Conference; Jun. 1, 1985; pp. 396-404, XP-000756796; IEEE.

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